Synthesis Report Synthesis options: The -a option is iCE40UP. The -t option is SG48. The -sp option is High-Performance_1.2V. The -p option is iCE40UP5K. ########################################################## ### Lattice Family : iCE40UP ### Device : iCE40UP5K ### Package : SG48 ### Speed : High-Performance_1.2V INFO - synthesis: User-Selected Strategy Settings Optimization goal = Area Top-level module name = rs232_receiver. Target frequency = 1.000000 MHz. Maximum fanout = 1000. Timing path count = 3 RWCheckOnRam = 0 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = auto (Default) Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE Output HDL file name = SerialTest_impl_1.vm. ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -sdc option: SDC file input is W:/projects/Ice40SerialTest/source/impl1.ldc. -path C:/lscc/radiant/1.0/ispfpga/ice40tp/data (searchpath added) -path W:/projects/Ice40SerialTest (searchpath added) -path W:/projects/Ice40SerialTest/ebr (searchpath added) -path W:/projects/Ice40SerialTest/impl_1 (searchpath added) Mixed language design Verilog design file = C:/lscc/radiant/1.0/ip/pmi/pmi.v Verilog design file = W:/projects/Ice40SerialTest/ebr/rtl/ebr.v VHDL library = pmi VHDL design file = C:/lscc/radiant/1.0/ip/pmi/pmi.vhd VHDL library = work VHDL design file = W:/projects/Ice40SerialTest/source/rs232_sender.vhd VHDL library = work VHDL design file = W:/projects/Ice40SerialTest/source/top.vhd VHDL library = work VHDL design file = W:/projects/Ice40SerialTest/source/rs232_receiver.vhd The -r option is OFF. [ Remove LOC Properties is OFF. ] Compile design. Compile Design Begin Analyzing Verilog file c:/lscc/radiant/1.0/ip/pmi/pmi.v. VERI-1482 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(1): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_add.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_add.v(50): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/adder/rtl/lscc_adder.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(2): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_complex_mult.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_complex_mult.v(52): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/complex_mult/rtl/lscc_complex_mult.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(3): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_dsp.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(4): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_mac.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_mac.v(52): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/mult_accumulate/rtl/lscc_mult_accumulate.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(5): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_multaddsub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_multaddsub.v(52): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/mult_add_sub/rtl/lscc_mult_add_sub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(6): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_mult.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_mult.v(51): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/multiplier/rtl/lscc_multiplier.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(7): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_ram_dp.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_ram_dp.v(47): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/ram_dp/rtl/lscc_ram_dp.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(8): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_ram_dq.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_ram_dq.v(45): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/ram_dq/rtl/lscc_ram_dq.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.v(9): analyzing included file c:/lscc/radiant/1.0/ip/pmi/pmi_sub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi_sub.v(50): analyzing included file c:/lscc/radiant/1.0/ip/pmi/../common/subtractor/rtl/lscc_subtractor.v. VERI-1328 Analyzing Verilog file w:/projects/ice40serialtest/ebr/rtl/ebr.v. VERI-1482 INFO - synthesis: w:/projects/ice40serialtest/ebr/rtl/ebr.v(9): analyzing included file w:/projects/ice40serialtest/ebr/rtl/core/lscc_ram_dq.v. VERI-1328 Analyzing VHDL file c:/lscc/radiant/1.0/ip/pmi/pmi.vhd. VHDL-1481 INFO - synthesis: c:/lscc/radiant/1.0/ip/pmi/pmi.vhd(4): analyzing package components. VHDL-1014 unit rs232_receiver is not yet analyzed. VHDL-1485 Analyzing VHDL file w:/projects/ice40serialtest/source/rs232_sender.vhd. VHDL-1481 INFO - synthesis: w:/projects/ice40serialtest/source/rs232_sender.vhd(12): analyzing entity rs232_sender. VHDL-1012 INFO - synthesis: w:/projects/ice40serialtest/source/rs232_sender.vhd(25): analyzing architecture rtl. VHDL-1010 unit rs232_receiver is not yet analyzed. VHDL-1485 Analyzing VHDL file w:/projects/ice40serialtest/source/rs232_receiver.vhd. VHDL-1481 INFO - synthesis: w:/projects/ice40serialtest/source/rs232_receiver.vhd(11): analyzing entity rs232_receiver. VHDL-1012 INFO - synthesis: w:/projects/ice40serialtest/source/rs232_receiver.vhd(21): analyzing architecture rtl. VHDL-1010 unit rs232_receiver is not yet analyzed. VHDL-1485 Analyzing VHDL file w:/projects/ice40serialtest/source/top.vhd. VHDL-1481 INFO - synthesis: w:/projects/ice40serialtest/source/top.vhd(8): analyzing entity top. VHDL-1012 INFO - synthesis: w:/projects/ice40serialtest/source/top.vhd(18): analyzing architecture rtl. VHDL-1010 ERROR - synthesis: w:/projects/ice40serialtest/source/top.vhd(71): ebr is not a component. VHDL-1235