Copyright 2015 Lattice Semiconductor Corporation, All Rights Reserved Mon Nov 19 22:19:25 2018 Command Line: par -w -n 1 -t 1 -s 1 -exp parPathBased=ON \ SerialTest_impl_1_map.udb SerialTest_impl_1.udb Cost Table Summary Level/ Number Worst Timing Worst Timing Run Run Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 57.453 0 2.454 0 12 Success * : Design saved. Total (real) run time for 1-seed: 12 secs par done! Lattice Place and Route Report for Design "SerialTest_impl_1_map.udb" Mon Nov 19 22:19:25 2018 Best Par Run PAR: Place And Route Radiant (64-bit) 1.0.1.350.6. Command Line: par -w -t 1 -exp parPathBased=ON SerialTest_impl_1_map.udb \ SerialTest_impl_1_par.dir/5_1.udb Loading SerialTest_impl_1_map.udb ... Loading device for application udb from file 'itpa08.nph' in environment: C:/lscc/radiant/1.0/ispfpga. Design: top Family: iCE40UP Device: iCE40UP5K Package: SG48 Performance Grade: High-Performance_1.2V Number of Signals: 395 Number of Connections: 1080 Device utilization summary: SLICE (est.) 107/2640 4% used LUT 202/5280 3% used REG 123/5280 2% used PIO 3/56 5% used 3/36 8% bonded IOLOGIC 2/56 3% used DSP 0/8 0% used I2C 0/2 0% used HFOSC 0/1 0% used LFOSC 0/1 0% used LEDDA_IP 0/1 0% used RGBA_DRV 1/1 100% used FILTER 0/2 0% used SRAM 1/4 25% used WARMBOOT 0/1 0% used SPI 0/2 0% used EBR 0/30 0% used PLL 0/1 0% used RGBOUTBUF 3/3 100% used I3C 0/2 0% used OPENDRAIN 0/3 0% used Pin Constraint Summary: 3 out of 3 pins locked (100% locked). Finished Placer Phase 0 (HIER). CPU time: 0 secs , REAL time: 0 secs .................. Finished Placer Phase 0 (AP). CPU time: 1 secs , REAL time: 0 secs Starting Placer Phase 1. REAL time: 0 secs .. .. .................... Placer score = 43433. Device SLICE utilization summary after final SLICE packing: SLICE 105/2640 3% used Finished Placer Phase 1. CPU time: 8 secs , REAL time: 8 secs Starting Placer Phase 2. . Placer score = 49661 Finished Placer Phase 2. CPU time: 8 secs , REAL time: 8 secs Clock Report Global Clocks : PRIMARY "clk_c" from comp "clk" on CLK_PIN site "35 (PR13B)", clk load = 74, ce load = 0, sr load = 0 PRIMARY : 1 out of 8 (12%) I/O Usage Summary (final): 3 out of 56 (5.4%) PIO sites used. 3 out of 36 (8.3%) bonded PIO sites used. Number of PIO comps: 3; differential: 0 Number of Vref pins used: 0 I/O Bank Usage Summary: +----------+---------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+---------------+------------+------------+------------+ | 0 | 1 / 14 ( 7%) | 3.3V | | | | 1 | 2 / 14 ( 14%) | 3.3V | | | | 2 | 0 / 8 ( 0%) | OFF | | | +----------+---------------+------------+------------+------------+ Total Placer CPU time: 8 secs , REAL time: 8 secs Writing design to file SerialTest_impl_1_par.dir/5_1.udb ... Start NBR router at 22:19:33 11/19/18 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in timing report. You should always run the timing tool to verify your design. ***************************************************************** Starting routing resource preassignment Preassignment Summary: -------------------------------------------------------------------------------- 177 connections routed with dedicated routing resources 1 global clock signals routed 251 connections routed (of 1033 total) (24.30%) --------------------------------------------------------- Clock routing summary: Primary clocks (1 used out of 8 available): #7 Signal "clk_c" Clock loads: 74 out of 74 routed (100.00%) --------------------------------------------------------- -------------------------------------------------------------------------------- Completed routing resource preassignment Start NBR section for initial routing at 22:19:33 11/19/18 Level 4, iteration 1 9(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 58.049ns/0.000ns; real time: 0 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 22:19:34 11/19/18 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 57.453ns/0.000ns; real time: 0 secs Start NBR section for setup/hold timing optimization with effort level 3 at 22:19:34 11/19/18 Start NBR section for re-routing at 22:19:35 11/19/18 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 2 secs Start NBR section for post-routing at 22:19:35 11/19/18 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack<setup> : 57.453ns Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only. --------------------------------------------------------- Clock routing summary: Primary clocks (1 used out of 8 available): #7 Signal "clk_c" Clock loads: 74 out of 74 routed (100.00%) --------------------------------------------------------- Total CPU time 3 secs Total REAL time: 4 secs Completely routed. End of route. 1033 routed (100.00%); 0 unrouted. Writing design to file SerialTest_impl_1_par.dir/5_1.udb ... All signals are completely routed. PAR_SUMMARY::Run status = Success PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = 57.453 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 2.454 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU Time: 12 secs Total REAL Time: 12 secs Peak Memory Usage: 115 MB par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2018 Lattice Semiconductor Corporation, All rights reserved.