Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant (64-bit) 1.0.1.350.6
Mon Nov 19 22:19:21 2018
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2018 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -db-file SerialTest_impl_1.udb -sethld -v 3 -endpoints 10 -u 10 -ports 10 -rpt-file SerialTest_impl_1_lse.twr
-----------------------------------------
Design: top
Family: iCE40UP
Device: iCE40UP5K
Package: SG48
Performance: High-Performance_1.2V
-----------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 DESIGN CHECKING
1.1 SDC Constraints
1.2 Combinational Loop
2 CLOCK SUMMARY
2.1 Clock clk
3 TIMING ANALYSIS SUMMARY
3.1 Overall (Setup and Hold)
3.1.1 Constraint Coverage
3.1.2 Timing Errors
3.1.3 Total Timing Score
3.2 Setup Summary Report
3.2.1 Setup Constraint Slack Summary
3.2.2 Setup Critical Endpoint Summary
3.3 Hold Summary Report
3.3.1 Hold Constraint Slack Summary
3.3.2 Hold Critical Endpoint Summary
3.4 Unconstrained Report
3.4.1 Unconstrained Start/End Points
3.4.2 Start/End Points Without Timing Constraints
4 DETAILED REPORT
4.1 Setup Detailed Report
4.1.1 Setup Path Details For Constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
4.2 Hold Detailed Report
4.2.1 Hold Path Details For Constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
=====================================================================
End of Table of Contents
=====================================================================
1 DESIGN CHECKING
1.1 SDC Constraints
create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
1.2 Combinational Loop
2 CLOCK SUMMARY
2.1 Clock "clk"
create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk | Target | 83.333 ns | 12.000 MHz
| Actual (all paths) | 25.723 ns | 38.876 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
3 TIMING ANALYSIS SUMMARY
3.1 Overall (Setup and Hold)
3.1.1 Constraint Coverage
Constraint Coverage: 97.5992%
3.1.2 Timing Errors
Timing Errors: 0 endpoints (setup), 0 endpoints (hold)
3.1.3 Total Timing Score
Total Negative Slack: 0.000 ns (setup), 0.000 ns (hold)
3.2 Setup Summary Report
3.2.1 Setup Constraint Slack Summary
-------------------------------------------------------------------------------------------------------------------------------------------
| | | | Actual (flop to flop) | |
SDC Constraint | Target | Slack | Levels | Period | Frequency | Items Scored | Timing Error
-------------------------------------------------------------------------------------------------------------------------------------------
| | | | | | |
create_clock -name {clk} -period 83.333
3333333333 [get_ports clk] | 83.333 ns | 57.610 ns | 24 | 25.723 ns | 38.876 MHz | 294 | 0
-------------------------------------------------------------------------------------------------------------------------------------------
3.2.2 Setup Critical Endpoint Summary
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
counter_451__i22/D | 57.610 ns
counter_451__i21/D | 58.626 ns
counter_451__i20/D | 59.642 ns
counter_451__i19/D | 60.658 ns
counter_451__i18/D | 61.674 ns
counter_451__i17/D | 62.690 ns
counter_451__i16/D | 63.706 ns
counter_451__i15/D | 64.722 ns
counter_451__i14/D | 65.738 ns
ram_ad__i13/D | 66.557 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
3.3 Hold Summary Report
3.3.1 Hold Constraint Slack Summary
-------------------------------------------------------------------------------------------------------------------------------------------
| | | | Actual (flop to flop) | |
SDC Constraint | Target | Slack | Levels | Period | Frequency | Items Scored | Timing Error
-------------------------------------------------------------------------------------------------------------------------------------------
| | | | | | |
create_clock -name {clk} -period 83.333
3333333333 [get_ports clk] | 0.000 ns | 1.683 ns | 1 | ---- | ---- | 294 | 0
-------------------------------------------------------------------------------------------------------------------------------------------
3.3.2 Hold Critical Endpoint Summary
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
ram/WREN | 1.683 ns
ram/DATAIN14 | 1.921 ns
ram/DATAIN13 | 1.921 ns
ram/DATAIN12 | 1.921 ns
ram/DATAIN11 | 1.921 ns
ram/DATAIN10 | 1.921 ns
ram/DATAIN9 | 1.921 ns
ram/DATAIN8 | 1.921 ns
ram/DATAIN7 | 1.921 ns
ram/DATAIN6 | 1.921 ns
-------------------------------------------------------
|
Hold # of endpoints with negative slack: | 0
|
-------------------------------------------------------
3.4 Unconstrained Report
3.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
-------------------------------------------------------------------
Listing 10 Start Points | Type
-------------------------------------------------------------------
ram/DATAOUT14 | No arrival or required
ram/DATAOUT13 | No arrival or required
ram/DATAOUT12 | No arrival or required
ram/DATAOUT11 | No arrival or required
ram/DATAOUT10 | No arrival or required
ram/DATAOUT9 | No arrival or required
ram/DATAOUT8 | No arrival or required
ram/DATAOUT7 | No arrival or required
ram/DATAOUT6 | No arrival or required
ram/DATAOUT5 | No arrival or required
-------------------------------------------------------------------
|
Number of unconstrained timing start po |
ints | 17
|
-------------------------------------------------------------------
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 1 End Points | Type
-------------------------------------------------------------------
\receiver/rx_latch_55/PADDI | No arrival time
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 1
|
-------------------------------------------------------------------
3.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 5 Start or End Points | Type
-------------------------------------------------------------------
txd | input
rxd | output
led_blue | output
led_green | output
led_red | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 5
|
-------------------------------------------------------------------
Registers without clock definition
Define the clock for these registers.
--------------------------------------------------
There is no instance satisfying reporting criteria
4 DETAILED REPORT
4.1 Setup Detailed Report
4.1.1 Setup path details for constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
----------------------------------------------------------------------
294 endpoints scored, 0 timing errors detected.
Minimum Pulse Width Report
--------------------------
MPW Cell : VFB_B
MPW Pin : CLOCK
MPW Period : 0.418 ns
Clock Period : 83.3333 ns
Period margin : 82.9153 ns (Passed)
--------------------------
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i22/D
Source Clock : clk
Destination Clock: clk
Logic Level : 24
Delay Ratio : 68.5% (route), 31.5% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 57.610 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 25.524
------------------------------------- ------
End-of-path arrival time( ns ) 27.536
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ---------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q FD1P3XZ CK_TO_Q_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.738 4.141 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
FA2 C1_TO_CO1_DELAY 0.344 4.485 2
n2209 NET DELAY 0.738 5.223 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
FA2 CI0_TO_CO0_DELAY 0.278 5.501 2
n3443 NET DELAY 0.738 6.239 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
FA2 CI1_TO_CO1_DELAY 0.278 6.517 2
n2211 NET DELAY 0.738 7.255 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
FA2 CI0_TO_CO0_DELAY 0.278 7.533 2
n3446 NET DELAY 0.738 8.271 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
FA2 CI1_TO_CO1_DELAY 0.278 8.549 2
n2213 NET DELAY 0.738 9.287 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
FA2 CI0_TO_CO0_DELAY 0.278 9.565 2
n3449 NET DELAY 0.738 10.303 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
FA2 CI1_TO_CO1_DELAY 0.278 10.581 2
n2215 NET DELAY 0.738 11.319 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
FA2 CI0_TO_CO0_DELAY 0.278 11.597 2
n3452 NET DELAY 0.738 12.335 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
FA2 CI1_TO_CO1_DELAY 0.278 12.613 2
n2217 NET DELAY 0.738 13.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
FA2 CI0_TO_CO0_DELAY 0.278 13.629 2
n3455 NET DELAY 0.738 14.367 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
FA2 CI1_TO_CO1_DELAY 0.278 14.645 2
n2219 NET DELAY 0.738 15.383 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
FA2 CI0_TO_CO0_DELAY 0.278 15.661 2
n3458 NET DELAY 0.738 16.399 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
FA2 CI1_TO_CO1_DELAY 0.278 16.677 2
n2221 NET DELAY 0.738 17.415 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
FA2 CI0_TO_CO0_DELAY 0.278 17.693 2
n3461 NET DELAY 0.738 18.431 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
FA2 CI1_TO_CO1_DELAY 0.278 18.709 2
n2223 NET DELAY 0.738 19.447 1
counter_451_add_4_17/CI0->counter_451_add_4_17/CO0
FA2 CI0_TO_CO0_DELAY 0.278 19.725 2
n3464 NET DELAY 0.738 20.463 1
counter_451_add_4_17/CI1->counter_451_add_4_17/CO1
FA2 CI1_TO_CO1_DELAY 0.278 20.741 2
n2225 NET DELAY 0.738 21.479 1
counter_451_add_4_19/CI0->counter_451_add_4_19/CO0
FA2 CI0_TO_CO0_DELAY 0.278 21.757 2
n3467 NET DELAY 0.738 22.495 1
counter_451_add_4_19/CI1->counter_451_add_4_19/CO1
FA2 CI1_TO_CO1_DELAY 0.278 22.773 2
n2227 NET DELAY 0.738 23.511 1
counter_451_add_4_21/CI0->counter_451_add_4_21/CO0
FA2 CI0_TO_CO0_DELAY 0.278 23.789 2
n3470 NET DELAY 0.738 24.527 1
counter_451_add_4_21/CI1->counter_451_add_4_21/CO1
FA2 CI1_TO_CO1_DELAY 0.278 24.805 2
n2229 NET DELAY 0.738 25.543 1
counter_451_add_4_23/CI0->counter_451_add_4_23/CO0
FA2 CI0_TO_CO0_DELAY 0.278 25.821 2
n3473 NET DELAY 0.738 26.559 1
counter_451_add_4_23/D1->counter_451_add_4_23/S1
FA2 D1_TO_S1_DELAY 0.477 27.036 1
n98 NET DELAY 0.500 27.536 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
++++Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i21/D
Source Clock : clk
Destination Clock: clk
Logic Level : 23
Delay Ratio : 68.3% (route), 31.7% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 58.626 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 24.508
------------------------------------- ------
End-of-path arrival time( ns ) 26.520
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ---------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q FD1P3XZ CK_TO_Q_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.738 4.141 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
FA2 C1_TO_CO1_DELAY 0.344 4.485 2
n2209 NET DELAY 0.738 5.223 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
FA2 CI0_TO_CO0_DELAY 0.278 5.501 2
n3443 NET DELAY 0.738 6.239 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
FA2 CI1_TO_CO1_DELAY 0.278 6.517 2
n2211 NET DELAY 0.738 7.255 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
FA2 CI0_TO_CO0_DELAY 0.278 7.533 2
n3446 NET DELAY 0.738 8.271 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
FA2 CI1_TO_CO1_DELAY 0.278 8.549 2
n2213 NET DELAY 0.738 9.287 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
FA2 CI0_TO_CO0_DELAY 0.278 9.565 2
n3449 NET DELAY 0.738 10.303 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
FA2 CI1_TO_CO1_DELAY 0.278 10.581 2
n2215 NET DELAY 0.738 11.319 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
FA2 CI0_TO_CO0_DELAY 0.278 11.597 2
n3452 NET DELAY 0.738 12.335 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
FA2 CI1_TO_CO1_DELAY 0.278 12.613 2
n2217 NET DELAY 0.738 13.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
FA2 CI0_TO_CO0_DELAY 0.278 13.629 2
n3455 NET DELAY 0.738 14.367 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
FA2 CI1_TO_CO1_DELAY 0.278 14.645 2
n2219 NET DELAY 0.738 15.383 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
FA2 CI0_TO_CO0_DELAY 0.278 15.661 2
n3458 NET DELAY 0.738 16.399 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
FA2 CI1_TO_CO1_DELAY 0.278 16.677 2
n2221 NET DELAY 0.738 17.415 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
FA2 CI0_TO_CO0_DELAY 0.278 17.693 2
n3461 NET DELAY 0.738 18.431 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
FA2 CI1_TO_CO1_DELAY 0.278 18.709 2
n2223 NET DELAY 0.738 19.447 1
counter_451_add_4_17/CI0->counter_451_add_4_17/CO0
FA2 CI0_TO_CO0_DELAY 0.278 19.725 2
n3464 NET DELAY 0.738 20.463 1
counter_451_add_4_17/CI1->counter_451_add_4_17/CO1
FA2 CI1_TO_CO1_DELAY 0.278 20.741 2
n2225 NET DELAY 0.738 21.479 1
counter_451_add_4_19/CI0->counter_451_add_4_19/CO0
FA2 CI0_TO_CO0_DELAY 0.278 21.757 2
n3467 NET DELAY 0.738 22.495 1
counter_451_add_4_19/CI1->counter_451_add_4_19/CO1
FA2 CI1_TO_CO1_DELAY 0.278 22.773 2
n2227 NET DELAY 0.738 23.511 1
counter_451_add_4_21/CI0->counter_451_add_4_21/CO0
FA2 CI0_TO_CO0_DELAY 0.278 23.789 2
n3470 NET DELAY 0.738 24.527 1
counter_451_add_4_21/CI1->counter_451_add_4_21/CO1
FA2 CI1_TO_CO1_DELAY 0.278 24.805 2
n2229 NET DELAY 0.738 25.543 1
counter_451_add_4_23/D0->counter_451_add_4_23/S0
FA2 D0_TO_S0_DELAY 0.477 26.020 1
n99 NET DELAY 0.500 26.520 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
++++Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i20/D
Source Clock : clk
Destination Clock: clk
Logic Level : 22
Delay Ratio : 68.1% (route), 31.9% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 59.642 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 23.492
------------------------------------- ------
End-of-path arrival time( ns ) 25.504
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ---------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q FD1P3XZ CK_TO_Q_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.738 4.141 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
FA2 C1_TO_CO1_DELAY 0.344 4.485 2
n2209 NET DELAY 0.738 5.223 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
FA2 CI0_TO_CO0_DELAY 0.278 5.501 2
n3443 NET DELAY 0.738 6.239 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
FA2 CI1_TO_CO1_DELAY 0.278 6.517 2
n2211 NET DELAY 0.738 7.255 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
FA2 CI0_TO_CO0_DELAY 0.278 7.533 2
n3446 NET DELAY 0.738 8.271 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
FA2 CI1_TO_CO1_DELAY 0.278 8.549 2
n2213 NET DELAY 0.738 9.287 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
FA2 CI0_TO_CO0_DELAY 0.278 9.565 2
n3449 NET DELAY 0.738 10.303 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
FA2 CI1_TO_CO1_DELAY 0.278 10.581 2
n2215 NET DELAY 0.738 11.319 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
FA2 CI0_TO_CO0_DELAY 0.278 11.597 2
n3452 NET DELAY 0.738 12.335 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
FA2 CI1_TO_CO1_DELAY 0.278 12.613 2
n2217 NET DELAY 0.738 13.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
FA2 CI0_TO_CO0_DELAY 0.278 13.629 2
n3455 NET DELAY 0.738 14.367 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
FA2 CI1_TO_CO1_DELAY 0.278 14.645 2
n2219 NET DELAY 0.738 15.383 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
FA2 CI0_TO_CO0_DELAY 0.278 15.661 2
n3458 NET DELAY 0.738 16.399 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
FA2 CI1_TO_CO1_DELAY 0.278 16.677 2
n2221 NET DELAY 0.738 17.415 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
FA2 CI0_TO_CO0_DELAY 0.278 17.693 2
n3461 NET DELAY 0.738 18.431 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
FA2 CI1_TO_CO1_DELAY 0.278 18.709 2
n2223 NET DELAY 0.738 19.447 1
counter_451_add_4_17/CI0->counter_451_add_4_17/CO0
FA2 CI0_TO_CO0_DELAY 0.278 19.725 2
n3464 NET DELAY 0.738 20.463 1
counter_451_add_4_17/CI1->counter_451_add_4_17/CO1
FA2 CI1_TO_CO1_DELAY 0.278 20.741 2
n2225 NET DELAY 0.738 21.479 1
counter_451_add_4_19/CI0->counter_451_add_4_19/CO0
FA2 CI0_TO_CO0_DELAY 0.278 21.757 2
n3467 NET DELAY 0.738 22.495 1
counter_451_add_4_19/CI1->counter_451_add_4_19/CO1
FA2 CI1_TO_CO1_DELAY 0.278 22.773 2
n2227 NET DELAY 0.738 23.511 1
counter_451_add_4_21/CI0->counter_451_add_4_21/CO0
FA2 CI0_TO_CO0_DELAY 0.278 23.789 2
n3470 NET DELAY 0.738 24.527 1
counter_451_add_4_21/D1->counter_451_add_4_21/S1
FA2 D1_TO_S1_DELAY 0.477 25.004 1
n100 NET DELAY 0.500 25.504 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
4.2 Hold Detailed Report
4.2.1 Hold path details for constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
----------------------------------------------------------------------
294 endpoints scored, 0 timing errors detected.
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_we_104/Q
Path End : ram/WREN
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 26.4% (route), 73.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.683 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 1.891
------------------------------------- -----
End-of-path arrival time( ns ) 3.903
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------- ----- ------------ ------
ram_we_104/CK->ram_we_104/Q FD1P3XZ CK_TO_Q_DELAY 1.391 3.403 1
ram_we NET DELAY 0.500 3.903 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
++++Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i12/Q
Path End : ram/DATAIN12
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 34.7% (route), 65.3% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.921 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.129
------------------------------------- -----
End-of-path arrival time( ns ) 4.141
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------- ----- ------------ ------
ram_di_i0_i12/CK->ram_di_i0_i12/Q FD1P3XZ CK_TO_Q_DELAY 1.391 3.403 2
ram_di[12] NET DELAY 0.738 4.141 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
++++Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i14/Q
Path End : ram/DATAIN14
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 34.7% (route), 65.3% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.921 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.129
------------------------------------- -----
End-of-path arrival time( ns ) 4.141
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------- ----- ------------ ------
ram_di_i0_i14/CK->ram_di_i0_i14/Q FD1P3XZ CK_TO_Q_DELAY 1.391 3.403 2
ram_di[14] NET DELAY 0.738 4.141 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad/B->clk_pad/O BB_B IOPAD_TO_PADDI_DELAY 0.510 0.510 126
clk_c NET DELAY 1.502 2.012 1
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++