Project Settings
Project Name proj_1 Device Name impl_1: Lattice iCE40UP : iCE40UP5K
Implementation Name impl_1 Top Module top
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 34 83 0 - 00m:04s - 19.11.2018
20:44:02
(premap)Complete 6 2 0 0m:00s 0m:01s 133MB 19.11.2018
20:44:06
(fpga_mapper)Complete 7 5 0 0m:01s 0m:01s 135MB 19.11.2018
20:44:08
Multi-srs Generator Complete19.11.2018
20:44:03

Area Summary
PADS 6 FLOPS 84
RAMS (v_ram) 0 CARRYS 20
LUTS (total_luts) 102

Timing Summary
Clock NameReq FreqEst FreqSlack
top|clk236.0 MHzNANA
System110.8 MHz94.2 MHz-1.593

Optimizations Summary
Combined Clock Conversion 1 / 0