Timing Report
Lattice Timing Report -  Setup  and Hold, Version Radiant (64-bit) 1.0.1.350.6

Mon Nov 19 22:19:38 2018

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2018 Lattice Semiconductor Corporation,  All rights reserved.

Command line:    timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt SerialTest_impl_1.twr SerialTest_impl_1.udb -gui

-----------------------------------------
Design:          top
Family:          iCE40UP
Device:          iCE40UP5K
Package:         SG48
Performance:     High-Performance_1.2V
-----------------------------------------


=====================================================================
                    Table of Contents
=====================================================================
  • 1 DESIGN CHECKING
  • 1.1 SDC Constraints
  • 1.2 Combinational Loop
  • 2 CLOCK SUMMARY
  • 2.1 Clock clk
  • 3 TIMING ANALYSIS SUMMARY
  • 3.1 Overall (Setup and Hold)
  • 3.1.1 Constraint Coverage
  • 3.1.2 Timing Errors
  • 3.1.3 Total Timing Score
  • 3.2 Setup Summary Report
  • 3.2.1 Setup Constraint Slack Summary
  • 3.2.2 Setup Critical Endpoint Summary
  • 3.3 Hold Summary Report
  • 3.3.1 Hold Constraint Slack Summary
  • 3.3.2 Hold Critical Endpoint Summary
  • 3.4 Unconstrained Report
  • 3.4.1 Unconstrained Start/End Points
  • 3.4.2 Start/End Points Without Timing Constraints
  • 4 DETAILED REPORT
  • 4.1 Setup Detailed Report
  • 4.1.1 Setup Path Details For Constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
  • 4.2 Hold Detailed Report
  • 4.2.1 Hold Path Details For Constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
  • ===================================================================== End of Table of Contents ===================================================================== 1 DESIGN CHECKING 1.1 SDC Constraints create_clock -name {clk} -period 83.3333333333333 [get_ports clk] 1.2 Combinational Loop 2 CLOCK SUMMARY 2.1 Clock "clk" create_clock -name {clk} -period 83.3333333333333 [get_ports clk] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk | Target | 83.333 ns | 12.000 MHz | Actual (all paths) | 25.880 ns | 38.640 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------ 3 TIMING ANALYSIS SUMMARY 3.1 Overall (Setup and Hold) 3.1.1 Constraint Coverage Constraint Coverage: 99.0676% 3.1.2 Timing Errors Timing Errors: 0 endpoints (setup), 0 endpoints (hold) 3.1.3 Total Timing Score Total Negative Slack: 0.000 ns (setup), 0.000 ns (hold) 3.2 Setup Summary Report 3.2.1 Setup Constraint Slack Summary ------------------------------------------------------------------------------------------------------------------------------------------- | | | | Actual (flop to flop) | | SDC Constraint | Target | Slack | Levels | Period | Frequency | Items Scored | Timing Error ------------------------------------------------------------------------------------------------------------------------------------------- | | | | | | | create_clock -name {clk} -period 83.333 3333333333 [get_ports clk] | 83.333 ns | 57.453 ns | 7 | 25.880 ns | 38.640 MHz | 240 | 0 ------------------------------------------------------------------------------------------------------------------------------------------- 3.2.2 Setup Critical Endpoint Summary ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- {ram_ad__i5/SR ram_ad__i6/SR} | 57.453 ns {ram_ad__i3/SR ram_ad__i4/SR} | 57.453 ns {ram_ad__i1/SR ram_ad__i2/SR} | 57.453 ns ram_ad__i0/SR | 57.453 ns {ram_ad__i11/SR ram_ad__i12/SR} | 58.049 ns ram_ad__i13/SR | 58.049 ns {ram_ad__i7/SR ram_ad__i8/SR} | 58.049 ns {ram_ad__i9/SR ram_ad__i10/SR} | 58.049 ns {ram_ad__i5/SP ram_ad__i6/SP} | 61.916 ns {ram_ad__i3/SP ram_ad__i4/SP} | 61.916 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 3.3 Hold Summary Report 3.3.1 Hold Constraint Slack Summary ------------------------------------------------------------------------------------------------------------------------------------------- | | | | Actual (flop to flop) | | SDC Constraint | Target | Slack | Levels | Period | Frequency | Items Scored | Timing Error ------------------------------------------------------------------------------------------------------------------------------------------- | | | | | | | create_clock -name {clk} -period 83.333 3333333333 [get_ports clk] | 0.000 ns | 2.454 ns | 1 | ---- | ---- | 240 | 0 ------------------------------------------------------------------------------------------------------------------------------------------- 3.3.2 Hold Critical Endpoint Summary ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- ram/DATAIN15 | 2.454 ns ram/DATAIN14 | 2.454 ns ram/MASKWREN2 | 2.454 ns ram/DATAIN7 | 3.103 ns ram/DATAIN6 | 3.103 ns ram/MASKWREN1 | 3.103 ns ram/MASKWREN0 | 3.103 ns sender/bit_counter_i1/D | 3.112 ns sender/shift_register_i3/D | 3.112 ns sender/shift_register_i4/D | 3.112 ns ------------------------------------------------------- | Hold # of endpoints with negative slack: | 0 | ------------------------------------------------------- 3.4 Unconstrained Report 3.4.1 Unconstrained Start/End Points Clocked but unconstrained timing start points ------------------------------------------------------------------- Listing 10 Start Points | Type ------------------------------------------------------------------- sender/tx_56/PADDO | No required time ram/DATAOUT15 | No arrival or required ram/DATAOUT14 | No arrival or required ram/DATAOUT13 | No arrival or required ram/DATAOUT12 | No arrival or required ram/DATAOUT11 | No arrival or required ram/DATAOUT10 | No arrival or required ram/DATAOUT9 | No arrival or required ram/DATAOUT8 | No arrival or required ram/DATAOUT7 | No arrival or required ------------------------------------------------------------------- | Number of unconstrained timing start po | ints | 18 | ------------------------------------------------------------------- Clocked but unconstrained timing end points ------------------------------------------------------------------- Listing 1 End Points | Type ------------------------------------------------------------------- receiver/rx_latch_55/PADDI | No arrival time ------------------------------------------------------------------- | Number of unconstrained timing end poin | ts | 1 | ------------------------------------------------------------------- 3.4.2 Start/End Points Without Timing Constraints I/O ports without constraint ---------------------------- Possible constraints to use on I/O ports are: set_input_delay, set_output_delay, set_max_delay, create_clock, create_generated_clock, ... ------------------------------------------------------------------- Listing 5 Start or End Points | Type ------------------------------------------------------------------- txd | input led_blue | output led_green | output led_red | output rxd | output ------------------------------------------------------------------- | Number of I/O ports without constraint | 5 | ------------------------------------------------------------------- Registers without clock definition Define the clock for these registers. -------------------------------------------------- There is no instance satisfying reporting criteria 4 DETAILED REPORT 4.1 Setup Detailed Report 4.1.1 Setup path details for constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk] ---------------------------------------------------------------------- 240 endpoints scored, 0 timing errors detected. Minimum Pulse Width Report -------------------------- MPW Cell : SRAM MPW Pin : CLOCK MPW Period : 0.418 ns Clock Period : 83.3333 ns Period margin : 82.9153 ns (Passed) -------------------------- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_ad__i13/Q Path End : {ram_ad__i5/SR ram_ad__i6/SR} Source Clock : clk Destination Clock: clk Logic Level : 7 Delay Ratio : 83.8% (route), 16.2% (logic) Clock Skew : 0.000 ns Setup Constraint : 83.333 ns Path Slack : 57.453 ns (Passed) Destination Clock Arrival Time (clk:R#2) 83.333 + Destination Clock Source Latency 0.000 - Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 - Setup Time 0.530 ------------------------------------------ ------- End-of-path required time( ns ) 88.823 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 25.350 ------------------------------------- ------ End-of-path arrival time( ns ) 31.370 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ ram_ad__i13/CK->ram_ad__i13/Q SLICE_R6C4D CLK_TO_Q0_DELAY 1.391 7.411 3 ram_ad[13] NET DELAY 3.192 10.603 1 i9_4_lut/B->i9_4_lut/Z SLICE_R4C4A B0_TO_F0_DELAY 0.450 11.053 1 n21 NET DELAY 3.563 14.616 1 i11_3_lut/B->i11_3_lut/Z SLICE_R8C4A B1_TO_F1_DELAY 0.477 15.093 5 n2595 NET DELAY 0.305 15.398 1 i1_2_lut_3_lut/C->i1_2_lut_3_lut/Z SLICE_R8C4B C0_TO_F0_DELAY 0.450 15.848 5 rs232_sender_stb_N_138 NET DELAY 3.881 19.729 1 i1_3_lut_4_lut/D->i1_3_lut_4_lut/Z SLICE_R10C4B D1_TO_F1_DELAY 0.450 20.179 2 n976 NET DELAY 2.768 22.947 1 i2_4_lut/D->i2_4_lut/Z SLICE_R9C4D D1_TO_F1_DELAY 0.450 23.397 9 n1526 NET DELAY 3.669 27.066 1 i939_3_lut_4_lut/A->i939_3_lut_4_lut/Z SLICE_R10C4C A1_TO_F1_DELAY 0.450 27.516 8 n1679 NET DELAY 3.854 31.370 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_ad__i13/Q Path End : {ram_ad__i3/SR ram_ad__i4/SR} Source Clock : clk Destination Clock: clk Logic Level : 7 Delay Ratio : 83.8% (route), 16.2% (logic) Clock Skew : 0.000 ns Setup Constraint : 83.333 ns Path Slack : 57.453 ns (Passed) Destination Clock Arrival Time (clk:R#2) 83.333 + Destination Clock Source Latency 0.000 - Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 - Setup Time 0.530 ------------------------------------------ ------- End-of-path required time( ns ) 88.823 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 25.350 ------------------------------------- ------ End-of-path arrival time( ns ) 31.370 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ ram_ad__i13/CK->ram_ad__i13/Q SLICE_R6C4D CLK_TO_Q0_DELAY 1.391 7.411 3 ram_ad[13] NET DELAY 3.192 10.603 1 i9_4_lut/B->i9_4_lut/Z SLICE_R4C4A B0_TO_F0_DELAY 0.450 11.053 1 n21 NET DELAY 3.563 14.616 1 i11_3_lut/B->i11_3_lut/Z SLICE_R8C4A B1_TO_F1_DELAY 0.477 15.093 5 n2595 NET DELAY 0.305 15.398 1 i1_2_lut_3_lut/C->i1_2_lut_3_lut/Z SLICE_R8C4B C0_TO_F0_DELAY 0.450 15.848 5 rs232_sender_stb_N_138 NET DELAY 3.881 19.729 1 i1_3_lut_4_lut/D->i1_3_lut_4_lut/Z SLICE_R10C4B D1_TO_F1_DELAY 0.450 20.179 2 n976 NET DELAY 2.768 22.947 1 i2_4_lut/D->i2_4_lut/Z SLICE_R9C4D D1_TO_F1_DELAY 0.450 23.397 9 n1526 NET DELAY 3.669 27.066 1 i939_3_lut_4_lut/A->i939_3_lut_4_lut/Z SLICE_R10C4C A1_TO_F1_DELAY 0.450 27.516 8 n1679 NET DELAY 3.854 31.370 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_ad__i13/Q Path End : {ram_ad__i1/SR ram_ad__i2/SR} Source Clock : clk Destination Clock: clk Logic Level : 7 Delay Ratio : 83.8% (route), 16.2% (logic) Clock Skew : 0.000 ns Setup Constraint : 83.333 ns Path Slack : 57.453 ns (Passed) Destination Clock Arrival Time (clk:R#2) 83.333 + Destination Clock Source Latency 0.000 - Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 - Setup Time 0.530 ------------------------------------------ ------- End-of-path required time( ns ) 88.823 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 25.350 ------------------------------------- ------ End-of-path arrival time( ns ) 31.370 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ ram_ad__i13/CK->ram_ad__i13/Q SLICE_R6C4D CLK_TO_Q0_DELAY 1.391 7.411 3 ram_ad[13] NET DELAY 3.192 10.603 1 i9_4_lut/B->i9_4_lut/Z SLICE_R4C4A B0_TO_F0_DELAY 0.450 11.053 1 n21 NET DELAY 3.563 14.616 1 i11_3_lut/B->i11_3_lut/Z SLICE_R8C4A B1_TO_F1_DELAY 0.477 15.093 5 n2595 NET DELAY 0.305 15.398 1 i1_2_lut_3_lut/C->i1_2_lut_3_lut/Z SLICE_R8C4B C0_TO_F0_DELAY 0.450 15.848 5 rs232_sender_stb_N_138 NET DELAY 3.881 19.729 1 i1_3_lut_4_lut/D->i1_3_lut_4_lut/Z SLICE_R10C4B D1_TO_F1_DELAY 0.450 20.179 2 n976 NET DELAY 2.768 22.947 1 i2_4_lut/D->i2_4_lut/Z SLICE_R9C4D D1_TO_F1_DELAY 0.450 23.397 9 n1526 NET DELAY 3.669 27.066 1 i939_3_lut_4_lut/A->i939_3_lut_4_lut/Z SLICE_R10C4C A1_TO_F1_DELAY 0.450 27.516 8 n1679 NET DELAY 3.854 31.370 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_ad__i13/Q Path End : ram_ad__i0/SR Source Clock : clk Destination Clock: clk Logic Level : 7 Delay Ratio : 83.8% (route), 16.2% (logic) Clock Skew : 0.000 ns Setup Constraint : 83.333 ns Path Slack : 57.453 ns (Passed) Destination Clock Arrival Time (clk:R#2) 83.333 + Destination Clock Source Latency 0.000 - Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 - Setup Time 0.530 ------------------------------------------ ------- End-of-path required time( ns ) 88.823 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 25.350 ------------------------------------- ------ End-of-path arrival time( ns ) 31.370 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ ram_ad__i13/CK->ram_ad__i13/Q SLICE_R6C4D CLK_TO_Q0_DELAY 1.391 7.411 3 ram_ad[13] NET DELAY 3.192 10.603 1 i9_4_lut/B->i9_4_lut/Z SLICE_R4C4A B0_TO_F0_DELAY 0.450 11.053 1 n21 NET DELAY 3.563 14.616 1 i11_3_lut/B->i11_3_lut/Z SLICE_R8C4A B1_TO_F1_DELAY 0.477 15.093 5 n2595 NET DELAY 0.305 15.398 1 i1_2_lut_3_lut/C->i1_2_lut_3_lut/Z SLICE_R8C4B C0_TO_F0_DELAY 0.450 15.848 5 rs232_sender_stb_N_138 NET DELAY 3.881 19.729 1 i1_3_lut_4_lut/D->i1_3_lut_4_lut/Z SLICE_R10C4B D1_TO_F1_DELAY 0.450 20.179 2 n976 NET DELAY 2.768 22.947 1 i2_4_lut/D->i2_4_lut/Z SLICE_R9C4D D1_TO_F1_DELAY 0.450 23.397 9 n1526 NET DELAY 3.669 27.066 1 i939_3_lut_4_lut/A->i939_3_lut_4_lut/Z SLICE_R10C4C A1_TO_F1_DELAY 0.450 27.516 8 n1679 NET DELAY 3.854 31.370 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_ad__i13/Q Path End : {ram_ad__i11/SR ram_ad__i12/SR} Source Clock : clk Destination Clock: clk Logic Level : 7 Delay Ratio : 83.4% (route), 16.6% (logic) Clock Skew : 0.000 ns Setup Constraint : 83.333 ns Path Slack : 58.049 ns (Passed) Destination Clock Arrival Time (clk:R#2) 83.333 + Destination Clock Source Latency 0.000 - Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 - Setup Time 0.530 ------------------------------------------ ------- End-of-path required time( ns ) 88.823 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 24.754 ------------------------------------- ------ End-of-path arrival time( ns ) 30.774 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ ram_ad__i13/CK->ram_ad__i13/Q SLICE_R6C4D CLK_TO_Q0_DELAY 1.391 7.411 3 ram_ad[13] NET DELAY 3.192 10.603 1 i9_4_lut/B->i9_4_lut/Z SLICE_R4C4A B0_TO_F0_DELAY 0.450 11.053 1 n21 NET DELAY 3.563 14.616 1 i11_3_lut/B->i11_3_lut/Z SLICE_R8C4A B1_TO_F1_DELAY 0.477 15.093 5 n2595 NET DELAY 0.305 15.398 1 i1_2_lut_3_lut/C->i1_2_lut_3_lut/Z SLICE_R8C4B C0_TO_F0_DELAY 0.450 15.848 5 rs232_sender_stb_N_138 NET DELAY 3.881 19.729 1 i1_3_lut_4_lut/D->i1_3_lut_4_lut/Z SLICE_R10C4B D1_TO_F1_DELAY 0.450 20.179 2 n976 NET DELAY 2.768 22.947 1 i2_4_lut/D->i2_4_lut/Z SLICE_R9C4D D1_TO_F1_DELAY 0.450 23.397 9 n1526 NET DELAY 3.669 27.066 1 i939_3_lut_4_lut/A->i939_3_lut_4_lut/Z SLICE_R10C4C A1_TO_F1_DELAY 0.450 27.516 8 n1679 NET DELAY 3.258 30.774 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_ad__i13/Q Path End : ram_ad__i13/SR Source Clock : clk Destination Clock: clk Logic Level : 7 Delay Ratio : 83.4% (route), 16.6% (logic) Clock Skew : 0.000 ns Setup Constraint : 83.333 ns Path Slack : 58.049 ns (Passed) Destination Clock Arrival Time (clk:R#2) 83.333 + Destination Clock Source Latency 0.000 - Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 - Setup Time 0.530 ------------------------------------------ ------- End-of-path required time( ns ) 88.823 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 24.754 ------------------------------------- ------ End-of-path arrival time( ns ) 30.774 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ ram_ad__i13/CK->ram_ad__i13/Q SLICE_R6C4D CLK_TO_Q0_DELAY 1.391 7.411 3 ram_ad[13] NET DELAY 3.192 10.603 1 i9_4_lut/B->i9_4_lut/Z SLICE_R4C4A B0_TO_F0_DELAY 0.450 11.053 1 n21 NET DELAY 3.563 14.616 1 i11_3_lut/B->i11_3_lut/Z SLICE_R8C4A B1_TO_F1_DELAY 0.477 15.093 5 n2595 NET DELAY 0.305 15.398 1 i1_2_lut_3_lut/C->i1_2_lut_3_lut/Z SLICE_R8C4B C0_TO_F0_DELAY 0.450 15.848 5 rs232_sender_stb_N_138 NET DELAY 3.881 19.729 1 i1_3_lut_4_lut/D->i1_3_lut_4_lut/Z SLICE_R10C4B D1_TO_F1_DELAY 0.450 20.179 2 n976 NET DELAY 2.768 22.947 1 i2_4_lut/D->i2_4_lut/Z SLICE_R9C4D D1_TO_F1_DELAY 0.450 23.397 9 n1526 NET DELAY 3.669 27.066 1 i939_3_lut_4_lut/A->i939_3_lut_4_lut/Z SLICE_R10C4C A1_TO_F1_DELAY 0.450 27.516 8 n1679 NET DELAY 3.258 30.774 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_ad__i13/Q Path End : {ram_ad__i7/SR ram_ad__i8/SR} Source Clock : clk Destination Clock: clk Logic Level : 7 Delay Ratio : 83.4% (route), 16.6% (logic) Clock Skew : 0.000 ns Setup Constraint : 83.333 ns Path Slack : 58.049 ns (Passed) Destination Clock Arrival Time (clk:R#2) 83.333 + Destination Clock Source Latency 0.000 - Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 - Setup Time 0.530 ------------------------------------------ ------- End-of-path required time( ns ) 88.823 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 24.754 ------------------------------------- ------ End-of-path arrival time( ns ) 30.774 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ ram_ad__i13/CK->ram_ad__i13/Q SLICE_R6C4D CLK_TO_Q0_DELAY 1.391 7.411 3 ram_ad[13] NET DELAY 3.192 10.603 1 i9_4_lut/B->i9_4_lut/Z SLICE_R4C4A B0_TO_F0_DELAY 0.450 11.053 1 n21 NET DELAY 3.563 14.616 1 i11_3_lut/B->i11_3_lut/Z SLICE_R8C4A B1_TO_F1_DELAY 0.477 15.093 5 n2595 NET DELAY 0.305 15.398 1 i1_2_lut_3_lut/C->i1_2_lut_3_lut/Z SLICE_R8C4B C0_TO_F0_DELAY 0.450 15.848 5 rs232_sender_stb_N_138 NET DELAY 3.881 19.729 1 i1_3_lut_4_lut/D->i1_3_lut_4_lut/Z SLICE_R10C4B D1_TO_F1_DELAY 0.450 20.179 2 n976 NET DELAY 2.768 22.947 1 i2_4_lut/D->i2_4_lut/Z SLICE_R9C4D D1_TO_F1_DELAY 0.450 23.397 9 n1526 NET DELAY 3.669 27.066 1 i939_3_lut_4_lut/A->i939_3_lut_4_lut/Z SLICE_R10C4C A1_TO_F1_DELAY 0.450 27.516 8 n1679 NET DELAY 3.258 30.774 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_ad__i13/Q Path End : {ram_ad__i9/SR ram_ad__i10/SR} Source Clock : clk Destination Clock: clk Logic Level : 7 Delay Ratio : 83.4% (route), 16.6% (logic) Clock Skew : 0.000 ns Setup Constraint : 83.333 ns Path Slack : 58.049 ns (Passed) Destination Clock Arrival Time (clk:R#2) 83.333 + Destination Clock Source Latency 0.000 - Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 - Setup Time 0.530 ------------------------------------------ ------- End-of-path required time( ns ) 88.823 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 24.754 ------------------------------------- ------ End-of-path arrival time( ns ) 30.774 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ ram_ad__i13/CK->ram_ad__i13/Q SLICE_R6C4D CLK_TO_Q0_DELAY 1.391 7.411 3 ram_ad[13] NET DELAY 3.192 10.603 1 i9_4_lut/B->i9_4_lut/Z SLICE_R4C4A B0_TO_F0_DELAY 0.450 11.053 1 n21 NET DELAY 3.563 14.616 1 i11_3_lut/B->i11_3_lut/Z SLICE_R8C4A B1_TO_F1_DELAY 0.477 15.093 5 n2595 NET DELAY 0.305 15.398 1 i1_2_lut_3_lut/C->i1_2_lut_3_lut/Z SLICE_R8C4B C0_TO_F0_DELAY 0.450 15.848 5 rs232_sender_stb_N_138 NET DELAY 3.881 19.729 1 i1_3_lut_4_lut/D->i1_3_lut_4_lut/Z SLICE_R10C4B D1_TO_F1_DELAY 0.450 20.179 2 n976 NET DELAY 2.768 22.947 1 i2_4_lut/D->i2_4_lut/Z SLICE_R9C4D D1_TO_F1_DELAY 0.450 23.397 9 n1526 NET DELAY 3.669 27.066 1 i939_3_lut_4_lut/A->i939_3_lut_4_lut/Z SLICE_R10C4C A1_TO_F1_DELAY 0.450 27.516 8 n1679 NET DELAY 3.258 30.774 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_ad__i13/Q Path End : {ram_ad__i5/SP ram_ad__i6/SP} Source Clock : clk Destination Clock: clk Logic Level : 6 Delay Ratio : 82.7% (route), 17.3% (logic) Clock Skew : 0.000 ns Setup Constraint : 83.333 ns Path Slack : 61.916 ns (Passed) Destination Clock Arrival Time (clk:R#2) 83.333 + Destination Clock Source Latency 0.000 - Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 - Setup Time 0.199 ------------------------------------------ ------- End-of-path required time( ns ) 89.154 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 21.218 ------------------------------------- ------ End-of-path arrival time( ns ) 27.238 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ ram_ad__i13/CK->ram_ad__i13/Q SLICE_R6C4D CLK_TO_Q0_DELAY 1.391 7.411 3 ram_ad[13] NET DELAY 3.192 10.603 1 i9_4_lut/B->i9_4_lut/Z SLICE_R4C4A B0_TO_F0_DELAY 0.450 11.053 1 n21 NET DELAY 3.563 14.616 1 i11_3_lut/B->i11_3_lut/Z SLICE_R8C4A B1_TO_F1_DELAY 0.477 15.093 5 n2595 NET DELAY 0.305 15.398 1 i1_2_lut_3_lut/C->i1_2_lut_3_lut/Z SLICE_R8C4B C0_TO_F0_DELAY 0.450 15.848 5 rs232_sender_stb_N_138 NET DELAY 3.881 19.729 1 i1_3_lut_4_lut/D->i1_3_lut_4_lut/Z SLICE_R10C4B D1_TO_F1_DELAY 0.450 20.179 2 n976 NET DELAY 2.768 22.947 1 i2_4_lut/D->i2_4_lut/Z SLICE_R9C4D D1_TO_F1_DELAY 0.450 23.397 9 n1526 NET DELAY 3.841 27.238 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_ad__i13/Q Path End : {ram_ad__i3/SP ram_ad__i4/SP} Source Clock : clk Destination Clock: clk Logic Level : 6 Delay Ratio : 82.7% (route), 17.3% (logic) Clock Skew : 0.000 ns Setup Constraint : 83.333 ns Path Slack : 61.916 ns (Passed) Destination Clock Arrival Time (clk:R#2) 83.333 + Destination Clock Source Latency 0.000 - Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 - Setup Time 0.199 ------------------------------------------ ------- End-of-path required time( ns ) 89.154 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 21.218 ------------------------------------- ------ End-of-path arrival time( ns ) 27.238 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ ram_ad__i13/CK->ram_ad__i13/Q SLICE_R6C4D CLK_TO_Q0_DELAY 1.391 7.411 3 ram_ad[13] NET DELAY 3.192 10.603 1 i9_4_lut/B->i9_4_lut/Z SLICE_R4C4A B0_TO_F0_DELAY 0.450 11.053 1 n21 NET DELAY 3.563 14.616 1 i11_3_lut/B->i11_3_lut/Z SLICE_R8C4A B1_TO_F1_DELAY 0.477 15.093 5 n2595 NET DELAY 0.305 15.398 1 i1_2_lut_3_lut/C->i1_2_lut_3_lut/Z SLICE_R8C4B C0_TO_F0_DELAY 0.450 15.848 5 rs232_sender_stb_N_138 NET DELAY 3.881 19.729 1 i1_3_lut_4_lut/D->i1_3_lut_4_lut/Z SLICE_R10C4B D1_TO_F1_DELAY 0.450 20.179 2 n976 NET DELAY 2.768 22.947 1 i2_4_lut/D->i2_4_lut/Z SLICE_R9C4D D1_TO_F1_DELAY 0.450 23.397 9 n1526 NET DELAY 3.841 27.238 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 4.2 Hold Detailed Report 4.2.1 Hold path details for constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk] ---------------------------------------------------------------------- 240 endpoints scored, 0 timing errors detected. +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_di_i0_i14/Q Path End : ram/DATAIN14 Source Clock : clk Destination Clock: clk Logic Level : 1 Delay Ratio : 47.7% (route), 52.3% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 2.454 ns (Passed) Destination Clock Arrival Time (clk:R#1) 0.000 + Destination Clock Source Latency 0.000 + Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 + Hold Time -0.208 ------------------------------------------ ------- End-of-path required time( ns ) 6.228 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 2.662 ------------------------------------- ----- End-of-path arrival time( ns ) 8.682 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ {ram_di_i0_i15/CK ram_di_i0_i14/CK}->ram_di_i0_i14/Q SLICE_R2C4D CLK_TO_Q1_DELAY 1.391 7.411 2 ram_di[14] NET DELAY 1.271 8.682 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_di_i0_i15/Q Path End : ram/DATAIN15 Source Clock : clk Destination Clock: clk Logic Level : 1 Delay Ratio : 47.7% (route), 52.3% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 2.454 ns (Passed) Destination Clock Arrival Time (clk:R#1) 0.000 + Destination Clock Source Latency 0.000 + Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 + Hold Time -0.208 ------------------------------------------ ------- End-of-path required time( ns ) 6.228 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 2.662 ------------------------------------- ----- End-of-path arrival time( ns ) 8.682 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ {ram_di_i0_i15/CK ram_di_i0_i14/CK}->ram_di_i0_i15/Q SLICE_R2C4D CLK_TO_Q0_DELAY 1.391 7.411 2 ram_di[15] NET DELAY 1.271 8.682 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_maskwe__i2/Q Path End : ram/MASKWREN2 Source Clock : clk Destination Clock: clk Logic Level : 1 Delay Ratio : 47.7% (route), 52.3% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 2.454 ns (Passed) Destination Clock Arrival Time (clk:R#1) 0.000 + Destination Clock Source Latency 0.000 + Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 + Hold Time -0.208 ------------------------------------------ ------- End-of-path required time( ns ) 6.228 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 2.662 ------------------------------------- ----- End-of-path arrival time( ns ) 8.682 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ {ram_maskwe__i2/CK ram_maskwe__i1/CK}->ram_maskwe__i2/Q SLICE_R2C4B CLK_TO_Q0_DELAY 1.391 7.411 3 ram_maskwe[3] NET DELAY 1.271 8.682 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_maskwe__i1/Q Path End : ram/MASKWREN1 Source Clock : clk Destination Clock: clk Logic Level : 1 Delay Ratio : 58.0% (route), 42.0% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 3.103 ns (Passed) Destination Clock Arrival Time (clk:R#1) 0.000 + Destination Clock Source Latency 0.000 + Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 + Hold Time -0.208 ------------------------------------------ ------- End-of-path required time( ns ) 6.228 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 3.311 ------------------------------------- ----- End-of-path arrival time( ns ) 9.331 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ {ram_maskwe__i2/CK ram_maskwe__i1/CK}->ram_maskwe__i1/Q SLICE_R2C4B CLK_TO_Q1_DELAY 1.391 7.411 3 ram_maskwe[1] NET DELAY 1.920 9.331 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_di_i0_i6/Q Path End : ram/DATAIN6 Source Clock : clk Destination Clock: clk Logic Level : 1 Delay Ratio : 58.0% (route), 42.0% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 3.103 ns (Passed) Destination Clock Arrival Time (clk:R#1) 0.000 + Destination Clock Source Latency 0.000 + Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 + Hold Time -0.208 ------------------------------------------ ------- End-of-path required time( ns ) 6.228 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 3.311 ------------------------------------- ----- End-of-path arrival time( ns ) 9.331 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ {ram_di_i0_i7/CK ram_di_i0_i6/CK}->ram_di_i0_i6/Q SLICE_R2C4A CLK_TO_Q1_DELAY 1.391 7.411 2 ram_di[6] NET DELAY 1.920 9.331 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_di_i0_i7/Q Path End : ram/DATAIN7 Source Clock : clk Destination Clock: clk Logic Level : 1 Delay Ratio : 58.0% (route), 42.0% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 3.103 ns (Passed) Destination Clock Arrival Time (clk:R#1) 0.000 + Destination Clock Source Latency 0.000 + Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 + Hold Time -0.208 ------------------------------------------ ------- End-of-path required time( ns ) 6.228 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 3.311 ------------------------------------- ----- End-of-path arrival time( ns ) 9.331 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ {ram_di_i0_i7/CK ram_di_i0_i6/CK}->ram_di_i0_i7/Q SLICE_R2C4A CLK_TO_Q0_DELAY 1.391 7.411 2 ram_di[7] NET DELAY 1.920 9.331 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_maskwe__i1/Q Path End : ram/MASKWREN0 Source Clock : clk Destination Clock: clk Logic Level : 1 Delay Ratio : 58.0% (route), 42.0% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 3.103 ns (Passed) Destination Clock Arrival Time (clk:R#1) 0.000 + Destination Clock Source Latency 0.000 + Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 + Hold Time -0.208 ------------------------------------------ ------- End-of-path required time( ns ) 6.228 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 3.311 ------------------------------------- ----- End-of-path arrival time( ns ) 9.331 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ {ram_maskwe__i2/CK ram_maskwe__i1/CK}->ram_maskwe__i1/Q SLICE_R2C4B CLK_TO_Q1_DELAY 1.391 7.411 3 ram_maskwe[1] NET DELAY 1.920 9.331 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_di_i0_i14/Q Path End : ram_di_i0_i14/D Source Clock : clk Destination Clock: clk Logic Level : 2 Delay Ratio : 40.8% (route), 59.2% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 3.112 ns (Passed) Destination Clock Arrival Time (clk:R#1) 0.000 + Destination Clock Source Latency 0.000 + Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 + Hold Time -0.000 ------------------------------------------ ------- End-of-path required time( ns ) 6.020 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 3.112 ------------------------------------- ----- End-of-path arrival time( ns ) 9.132 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ {ram_di_i0_i15/CK ram_di_i0_i14/CK}->ram_di_i0_i14/Q SLICE_R2C4D CLK_TO_Q1_DELAY 1.391 7.411 2 ram_di[14] NET DELAY 1.271 8.682 1 i12_4_lut_adj_20/D->i12_4_lut_adj_20/Z SLICE_R2C4D D1_TO_F1_DELAY 0.450 9.132 1 n2561 NET DELAY 0.000 9.132 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_di_i0_i7/Q Path End : ram_di_i0_i7/D Source Clock : clk Destination Clock: clk Logic Level : 2 Delay Ratio : 40.8% (route), 59.2% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 3.112 ns (Passed) Destination Clock Arrival Time (clk:R#1) 0.000 + Destination Clock Source Latency 0.000 + Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 + Hold Time -0.000 ------------------------------------------ ------- End-of-path required time( ns ) 6.020 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 3.112 ------------------------------------- ----- End-of-path arrival time( ns ) 9.132 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ {ram_di_i0_i7/CK ram_di_i0_i6/CK}->ram_di_i0_i7/Q SLICE_R2C4A CLK_TO_Q0_DELAY 1.391 7.411 2 ram_di[7] NET DELAY 1.271 8.682 1 i12_4_lut_adj_21/D->i12_4_lut_adj_21/Z SLICE_R2C4A D0_TO_F0_DELAY 0.450 9.132 1 n2537 NET DELAY 0.000 9.132 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 ++++Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : ram_di_i0_i6/Q Path End : ram_di_i0_i6/D Source Clock : clk Destination Clock: clk Logic Level : 2 Delay Ratio : 40.8% (route), 59.2% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 3.112 ns (Passed) Destination Clock Arrival Time (clk:R#1) 0.000 + Destination Clock Source Latency 0.000 + Destination Clock Uncertainty 0.000 + Destination Clock Path Delay 6.020 + Hold Time -0.000 ------------------------------------------ ------- End-of-path required time( ns ) 6.020 Source Clock Arrival Time (clk:R#1) 0.000 + Source Clock Source Latency 0.000 + Source Clock Path Delay 6.020 + Data Path Delay 3.112 ------------------------------------- ----- End-of-path arrival time( ns ) 9.132 Source Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 Data path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- --------------- ----- ------------ ------ {ram_di_i0_i7/CK ram_di_i0_i6/CK}->ram_di_i0_i6/Q SLICE_R2C4A CLK_TO_Q1_DELAY 1.391 7.411 2 ram_di[6] NET DELAY 1.271 8.682 1 i12_4_lut_adj_23/D->i12_4_lut_adj_23/Z SLICE_R2C4A D1_TO_F1_DELAY 0.450 9.132 1 n2539 NET DELAY 0.000 9.132 1 Destination Clock Path Name Cell/Site Name Delay Name Delay Arrival Time Fanout ---------------------------------------- -------------- -------------------- ----- ------------ ------ clk top CLOCK LATENCY 0.000 0.000 1 clk NET DELAY 0.000 0.000 1 clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO_35 IOPAD_TO_PADDI_DELAY 0.510 0.510 74 clk_c NET DELAY 5.510 6.020 1 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

















































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