Synthesis Report
#Build: Synplify Pro (R) M-2017.03LR-SP1-1, Build 229R, Nov 10 2017
#install: C:\lscc\radiant\1.0\synpbase
#OS: Windows 8 6.2
#Hostname: DESKTOP-433C5TG

# Mon Nov 19 20:43:58 2018

#Implementation: impl_1

Synopsys HDL Compiler, version comp2017q2p1, Build 338R, built Nov 10 2017
@N|Running in 64-bit mode
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys VHDL Compiler, version comp2017q2p1, Build 338R, built Nov 10 2017
@N|Running in 64-bit mode
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@N: CD720 :"C:\lscc\radiant\1.0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ps
Pre Loading Built-In Library pmi ...
@N:"W:\projects\Ice40SerialTest\source\top.vhd":8:7:8:9|Top entity is set to top.
VHDL syntax check successful!

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)


Process completed successfully.
# Mon Nov 19 20:44:00 2018

###########################################################]
Synopsys Verilog Compiler, version comp2017q2p1, Build 338R, built Nov 10 2017
@N|Running in 64-bit mode
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"C:\lscc\radiant\1.0\synpbase\lib\generic\ice40up.v" (library work)
@I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\radiant\1.0\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\lscc\radiant\1.0\ip\pmi\pmi.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_add.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi_add.v":"C:\lscc\radiant\1.0\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\1.0\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
@N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v":89:11:89:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_complex_mult.v":98:11:98:22|Read directive translate_on.
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_dsp.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v":"C:\lscc\radiant\1.0\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
@N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v":91:11:91:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mac.v":106:11:106:22|Read directive translate_on.
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\1.0\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
@N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v":88:11:88:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_multaddsub.v":97:11:97:22|Read directive translate_on.
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v":"C:\lscc\radiant\1.0\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
@N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v":84:11:84:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_mult.v":93:11:93:22|Read directive translate_on.
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\1.0\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v" (library work)
@N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":95:11:95:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":150:11:150:22|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":194:11:194:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dp.v":201:11:201:22|Read directive translate_on.
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\1.0\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v" (library work)
@N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":82:11:82:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":91:11:91:22|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":129:11:129:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\1.0\ip\pmi\pmi_ram_dq.v":136:11:136:22|Read directive translate_on.
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi.v":"C:\lscc\radiant\1.0\ip\pmi\pmi_sub.v" (library work)
@I:"C:\lscc\radiant\1.0\ip\pmi\pmi_sub.v":"C:\lscc\radiant\1.0\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
Verilog syntax check successful!

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)


Process completed successfully.
# Mon Nov 19 20:44:00 2018

###########################################################]
@N: CD720 :"C:\lscc\radiant\1.0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ps
@N:"W:\projects\Ice40SerialTest\source\top.vhd":8:7:8:9|Top entity is set to top.
VHDL syntax check successful!
@N: CD630 :"W:\projects\Ice40SerialTest\source\top.vhd":8:7:8:9|Synthesizing work.top.rtl.
@N: CD233 :"W:\projects\Ice40SerialTest\source\top.vhd":47:17:47:18|Using sequential encoding for type state_type.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":28:8:28:21|Signal led_latch_blue is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":30:8:30:20|Signal led_latch_red is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Signal ram_ad is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":34:8:34:13|Signal ram_di is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":35:8:35:17|Signal ram_maskwe is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":36:8:36:13|Signal ram_we is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":37:8:37:13|Signal ram_cs is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":38:8:38:13|Signal ram_ck is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":39:8:39:16|Signal ram_stdby is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":40:8:40:16|Signal ram_sleep is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"W:\projects\Ice40SerialTest\source\top.vhd":41:8:41:19|Signal ram_pwroff_n is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"W:\projects\Ice40SerialTest\source\rs232_receiver.vhd":11:7:11:20|Synthesizing work.rs232_receiver.rtl.
@N: CD233 :"W:\projects\Ice40SerialTest\source\rs232_receiver.vhd":24:18:24:19|Using sequential encoding for type state_type.
Post processing for work.rs232_receiver.rtl
@N: CD630 :"W:\projects\Ice40SerialTest\source\rs232_sender.vhd":12:7:12:18|Synthesizing work.rs232_sender.rtl.
@N: CD233 :"W:\projects\Ice40SerialTest\source\rs232_sender.vhd":28:18:28:19|Using sequential encoding for type state_type.
Post processing for work.rs232_sender.rtl
Post processing for work.top.rtl
@W: CL240 :"W:\projects\Ice40SerialTest\source\top.vhd":41:8:41:19|Signal ram_pwroff_n is floating; a simulation mismatch is possible.
@W: CL240 :"W:\projects\Ice40SerialTest\source\top.vhd":40:8:40:16|Signal ram_sleep is floating; a simulation mismatch is possible.
@W: CL240 :"W:\projects\Ice40SerialTest\source\top.vhd":39:8:39:16|Signal ram_stdby is floating; a simulation mismatch is possible.
@W: CL240 :"W:\projects\Ice40SerialTest\source\top.vhd":38:8:38:13|Signal ram_ck is floating; a simulation mismatch is possible.
@W: CL240 :"W:\projects\Ice40SerialTest\source\top.vhd":37:8:37:13|Signal ram_cs is floating; a simulation mismatch is possible.
@W: CL240 :"W:\projects\Ice40SerialTest\source\top.vhd":36:8:36:13|Signal ram_we is floating; a simulation mismatch is possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":35:8:35:17|Bit 0 of signal ram_maskwe is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":35:8:35:17|Bit 1 of signal ram_maskwe is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":35:8:35:17|Bit 2 of signal ram_maskwe is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":35:8:35:17|Bit 3 of signal ram_maskwe is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 0 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 1 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 2 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 3 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 4 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 5 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 6 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 7 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 8 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 9 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 10 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 11 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 12 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL252 :"W:\projects\Ice40SerialTest\source\top.vhd":33:8:33:13|Bit 13 of signal ram_ad is floating -- simulation mismatch possible.
@W: CL240 :"W:\projects\Ice40SerialTest\source\top.vhd":30:8:30:20|Signal led_latch_red is floating; a simulation mismatch is possible.
@W: CL240 :"W:\projects\Ice40SerialTest\source\top.vhd":28:8:28:21|Signal led_latch_blue is floating; a simulation mismatch is possible.
@W: CL167 :"W:\projects\Ice40SerialTest\source\top.vhd":69:1:69:6|Input rgb0pwm of instance my_rgb is floating
@W: CL167 :"W:\projects\Ice40SerialTest\source\top.vhd":69:1:69:6|Input rgb2pwm of instance my_rgb is floating
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 0 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 1 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 2 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 3 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 4 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 5 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 6 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 7 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 8 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 9 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 10 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 11 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 12 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 13 of input ad of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 0 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 1 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 2 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 3 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 4 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 5 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 6 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 7 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 8 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 9 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 10 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 11 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 12 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 13 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 14 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 15 of input di of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 0 of input maskwe of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 1 of input maskwe of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 2 of input maskwe of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Bit 3 of input maskwe of instance ram is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL167 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Input we of instance ram is floating
@W: CL167 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Input cs of instance ram is floating
@W: CL167 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Input ck of instance ram is floating
@W: CL167 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Input stdby of instance ram is floating
@W: CL167 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Input sleep of instance ram is floating
@W: CL167 :"W:\projects\Ice40SerialTest\source\top.vhd":55:1:55:3|Input pwroff_n of instance ram is floating
@N: CL201 :"W:\projects\Ice40SerialTest\source\rs232_sender.vhd":45:4:45:5|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W: CL249 :"W:\projects\Ice40SerialTest\source\rs232_sender.vhd":45:4:45:5|Initial value is not supported on state machine state
@N: CL201 :"W:\projects\Ice40SerialTest\source\rs232_receiver.vhd":40:4:40:5|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W: CL249 :"W:\projects\Ice40SerialTest\source\rs232_receiver.vhd":40:4:40:5|Initial value is not supported on state machine state
@N: CL189 :"W:\projects\Ice40SerialTest\source\top.vhd":102:2:102:3|Register bit reset_counter(1) is always 1.
@W: CL260 :"W:\projects\Ice40SerialTest\source\top.vhd":102:2:102:3|Pruning register bit 1 of reset_counter(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL189 :"W:\projects\Ice40SerialTest\source\top.vhd":102:2:102:3|Register bit reset_counter(0) is always 1.
@W: CL177 :"W:\projects\Ice40SerialTest\source\top.vhd":116:2:116:3|Sharing sequential element state. Add a syn_preserve attribute to the element to prevent sharing.

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)


Process completed successfully.
# Mon Nov 19 20:44:01 2018

###########################################################]
Synopsys Netlist Linker, version comp2017q2p1, Build 338R, built Nov 10 2017
@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Nov 19 20:44:02 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Nov 19 20:44:02 2018

###########################################################]
Synopsys Netlist Linker, version comp2017q2p1, Build 338R, built Nov 10 2017
@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Nov 19 20:44:03 2018

###########################################################]
Pre-mapping Report

# Mon Nov 19 20:44:04 2018

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1868R, Built Nov 13 2017 02:40:05
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version M-2017.03LR-SP1-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A: MF827 |No constraint file specified.
@L: W:\projects\Ice40SerialTest\impl_1\SerialTest_impl_1_scck.rpt 
Printing clock  summary report in "W:\projects\Ice40SerialTest\impl_1\SerialTest_impl_1_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)

@W: BN114 :"w:\projects\ice40serialtest\source\top.vhd":55:1:55:3|Removing instance ram (in view: work.top(rtl)) of black box view:work.SP256K(syn_black_box) because it does not drive other instances.
@N: BN362 :"w:\projects\ice40serialtest\source\rs232_sender.vhd":45:4:45:5|Removing sequential instance busy (in view: work.rs232_sender_12000000_115200(rtl)) of type view:PrimLib.sdffrse(prim) because it does not drive other instances.
syn_allowed_resources : blockrams=30  set on top level netlist top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)



Clock Summary
******************

          Start       Requested     Requested     Clock        Clock                     Clock
Level     Clock       Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------
0 -       System      1.0 MHz       1000.000      system       system_clkgroup           0    
                                                                                              
0 -       top|clk     121.8 MHz     8.209         inferred     Autoconstr_clkgroup_0     88   
==============================================================================================

@W: MT530 :"w:\projects\ice40serialtest\source\rs232_sender.vhd":45:4:45:5|Found inferred clock top|clk which controls 88 sequential elements including sender.state[0:3]. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file W:\projects\Ice40SerialTest\impl_1\SerialTest_impl_1.sap.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)

Encoding state machine state[0:3] (in view: work.rs232_sender_12000000_115200(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MO225 :"w:\projects\ice40serialtest\source\rs232_sender.vhd":45:4:45:5|There are no possible illegal states for state machine state[0:3] (in view: work.rs232_sender_12000000_115200(rtl)); safe FSM implementation is not required.
Encoding state machine state[0:3] (in view: work.rs232_receiver_12000000_115200(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MO225 :"w:\projects\ice40serialtest\source\rs232_receiver.vhd":40:4:40:5|There are no possible illegal states for state machine state[0:3] (in view: work.rs232_receiver_12000000_115200(rtl)); safe FSM implementation is not required.

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 133MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Nov 19 20:44:06 2018

###########################################################]
Map & Optimize Report

# Mon Nov 19 20:44:06 2018

Synopsys Lattice Technology Mapper, Version maplat, Build 1868R, Built Nov 13 2017 02:40:05
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version M-2017.03LR-SP1-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled
@W: FX1039 :"w:\projects\ice40serialtest\source\rs232_sender.vhd":45:4:45:5|User-specified initial value defined for instance sender.bit_counter[2:0] is being ignored. 
@W: FX1039 :"w:\projects\ice40serialtest\source\rs232_sender.vhd":45:4:45:5|User-specified initial value defined for instance sender.baudrate_counter[6:0] is being ignored. 
@W: FX1039 :"w:\projects\ice40serialtest\source\rs232_sender.vhd":45:4:45:5|User-specified initial value defined for instance sender.shift_register[7:0] is being ignored. 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 133MB)

Encoding state machine state[0:3] (in view: work.rs232_sender_12000000_115200(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MO225 :"w:\projects\ice40serialtest\source\rs232_sender.vhd":45:4:45:5|There are no possible illegal states for state machine state[0:3] (in view: work.rs232_sender_12000000_115200(rtl)); safe FSM implementation is not required.
Encoding state machine state[0:3] (in view: work.rs232_receiver_12000000_115200(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MO225 :"w:\projects\ice40serialtest\source\rs232_receiver.vhd":40:4:40:5|There are no possible illegal states for state machine state[0:3] (in view: work.rs232_receiver_12000000_115200(rtl)); safe FSM implementation is not required.

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)


Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -2.28ns		 130 /        84
   2		0h:00m:00s		    -2.28ns		 128 /        84
   3		0h:00m:00s		    -2.28ns		 128 /        84

   4		0h:00m:00s		    -2.28ns		 128 /        84
   5		0h:00m:00s		    -1.63ns		 132 /        84


   6		0h:00m:00s		    -1.20ns		 132 /        84

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 134MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 84 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001       clk                 port                   84         led_latch_green
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 134MB)

Writing Analyst data base W:\projects\Ice40SerialTest\impl_1\synwork\SerialTest_impl_1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

Writing constraint files

Finished Writing constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

Writing Verilog Simulation files
Writing XDC file W:\projects\Ice40SerialTest\impl_1\SerialTest_impl_1.xdc

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 132MB peak: 135MB)


Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)

@W: MT246 :"w:\projects\ice40serialtest\source\top.vhd":69:1:69:6|Blackbox RGB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock top|clk with period 4.24ns. Please declare a user-defined clock on object "p:clk"


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Nov 19 20:44:08 2018
#


Top view:               top
Requested Frequency:    236.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -1.593

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
top|clk            236.0 MHz     NA            4.238         NA            NA         inferred     Autoconstr_clkgroup_0
System             110.8 MHz     94.2 MHz      9.027         10.620        -1.593     system       system_clkgroup      
========================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------
System    System  |  9.027       -1.593  |  No paths    -      |  No paths    -      |  No paths    -    
=========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                  Arrival           
Instance                         Reference     Type        Pin     Net                     Time        Slack 
                                 Clock                                                                       
-------------------------------------------------------------------------------------------------------------
sender.baudrate_counter[0]       System        FD1P3JZ     Q       baudrate_counter[0]     0.796       -1.593
sender.baudrate_counter[3]       System        FD1P3IZ     Q       baudrate_counter[3]     0.796       -1.521
sender.baudrate_counter[4]       System        FD1P3IZ     Q       baudrate_counter[4]     0.796       -1.490
sender.baudrate_counter[5]       System        FD1P3JZ     Q       baudrate_counter[5]     0.796       -1.397
receiver.baudrate_counter[0]     System        FD1P3JZ     Q       baudrate_counter[0]     0.796       0.243 
receiver.baudrate_counter[1]     System        FD1P3JZ     Q       baudrate_counter[1]     0.796       0.243 
sender.baudrate_counter[1]       System        FD1P3JZ     Q       baudrate_counter[1]     0.796       0.243 
receiver.baudrate_counter[2]     System        FD1P3IZ     Q       baudrate_counter[2]     0.796       0.316 
sender.baudrate_counter[2]       System        FD1P3JZ     Q       baudrate_counter[2]     0.796       0.316 
receiver.baudrate_counter[3]     System        FD1P3DZ     Q       baudrate_counter[3]     0.796       0.316 
=============================================================================================================


Ending Points with Worst Slack
******************************

                                 Starting                                                    Required           
Instance                         Reference     Type        Pin     Net                       Time         Slack 
                                 Clock                                                                          
----------------------------------------------------------------------------------------------------------------
sender.bit_counter[0]            System        FD1P3DZ     D       bit_counter               8.872        -1.593
sender.bit_counter[1]            System        FD1P3JZ     D       bit_counter_RNO[1]        8.872        -1.593
sender.bit_counter[2]            System        FD1P3JZ     D       bit_counter_RNO[2]        8.872        -1.593
receiver.baudrate_counter[0]     System        FD1P3JZ     D       baudrate_counter_8[0]     8.872        0.243 
receiver.baudrate_counter[1]     System        FD1P3JZ     D       baudrate_counter_8[1]     8.872        0.243 
receiver.baudrate_counter[2]     System        FD1P3IZ     D       baudrate_counter_8[2]     8.872        0.243 
receiver.baudrate_counter[5]     System        FD1P3JZ     D       baudrate_counter_8[5]     8.872        0.243 
receiver.baudrate_counter[6]     System        FD1P3IZ     D       baudrate_counter_8[6]     8.872        0.243 
receiver.bit_counter[0]          System        FD1P3DZ     D       bit_counter               8.872        0.243 
receiver.bit_counter[1]          System        FD1P3DZ     D       bit_counter_0             8.872        0.243 
================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      9.027
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         8.872

    - Propagation time:                      10.464
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -1.593

    Number of logic level(s):                4
    Starting point:                          sender.baudrate_counter[0] / Q
    Ending point:                            sender.bit_counter[1] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                    Type        Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
sender.baudrate_counter[0]              FD1P3JZ     Q        Out     0.796     0.796       -         
baudrate_counter[0]                     Net         -        -       1.599     -           3         
sender.baudrate_counter_RNI48I41[0]     LUT4        A        In      -         2.395       -         
sender.baudrate_counter_RNI48I41[0]     LUT4        Z        Out     0.661     3.056       -         
un1_state7_i_o2_4                       Net         -        -       1.371     -           2         
sender.baudrate_counter_RNI7UVV1[1]     LUT4        D        In      -         4.427       -         
sender.baudrate_counter_RNI7UVV1[1]     LUT4        Z        Out     0.465     4.893       -         
N_103_0                                 Net         -        -       1.371     -           18        
sender.bit_counter_RNO_0[1]             LUT4        A        In      -         6.263       -         
sender.bit_counter_RNO_0[1]             LUT4        Z        Out     0.661     6.925       -         
bit_counter_7_i_out                     Net         -        -       1.371     -           1         
sender.bit_counter_RNO[1]               LUT4        A        In      -         8.296       -         
sender.bit_counter_RNO[1]               LUT4        Z        Out     0.661     8.957       -         
bit_counter_RNO[1]                      Net         -        -       1.507     -           1         
sender.bit_counter[1]                   FD1P3JZ     D        In      -         10.464      -         
=====================================================================================================
Total path delay (propagation time + setup) of 10.619 is 3.400(32.0%) logic and 7.219(68.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      9.027
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         8.872

    - Propagation time:                      10.464
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -1.593

    Number of logic level(s):                4
    Starting point:                          sender.baudrate_counter[0] / Q
    Ending point:                            sender.bit_counter[0] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                    Type        Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
sender.baudrate_counter[0]              FD1P3JZ     Q        Out     0.796     0.796       -         
baudrate_counter[0]                     Net         -        -       1.599     -           3         
sender.baudrate_counter_RNI48I41[0]     LUT4        A        In      -         2.395       -         
sender.baudrate_counter_RNI48I41[0]     LUT4        Z        Out     0.661     3.056       -         
un1_state7_i_o2_4                       Net         -        -       1.371     -           2         
sender.baudrate_counter_RNI7UVV1[1]     LUT4        D        In      -         4.427       -         
sender.baudrate_counter_RNI7UVV1[1]     LUT4        Z        Out     0.465     4.893       -         
N_103_0                                 Net         -        -       1.371     -           18        
sender.state_RNIOEFQ2[0]                LUT4        A        In      -         6.263       -         
sender.state_RNIOEFQ2[0]                LUT4        Z        Out     0.661     6.925       -         
bit_counter_1_sqmuxa                    Net         -        -       1.371     -           3         
sender.bit_counter_RNO[0]               LUT4        A        In      -         8.296       -         
sender.bit_counter_RNO[0]               LUT4        Z        Out     0.661     8.957       -         
bit_counter                             Net         -        -       1.507     -           1         
sender.bit_counter[0]                   FD1P3DZ     D        In      -         10.464      -         
=====================================================================================================
Total path delay (propagation time + setup) of 10.619 is 3.400(32.0%) logic and 7.219(68.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      9.027
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         8.872

    - Propagation time:                      10.464
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -1.593

    Number of logic level(s):                4
    Starting point:                          sender.baudrate_counter[0] / Q
    Ending point:                            sender.bit_counter[2] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                    Type        Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
sender.baudrate_counter[0]              FD1P3JZ     Q        Out     0.796     0.796       -         
baudrate_counter[0]                     Net         -        -       1.599     -           3         
sender.baudrate_counter_RNI48I41[0]     LUT4        A        In      -         2.395       -         
sender.baudrate_counter_RNI48I41[0]     LUT4        Z        Out     0.661     3.056       -         
un1_state7_i_o2_4                       Net         -        -       1.371     -           2         
sender.baudrate_counter_RNI7UVV1[1]     LUT4        D        In      -         4.427       -         
sender.baudrate_counter_RNI7UVV1[1]     LUT4        Z        Out     0.465     4.893       -         
N_103_0                                 Net         -        -       1.371     -           18        
sender.bit_counter_RNO_0[2]             LUT4        A        In      -         6.263       -         
sender.bit_counter_RNO_0[2]             LUT4        Z        Out     0.661     6.925       -         
N_55                                    Net         -        -       1.371     -           1         
sender.bit_counter_RNO[2]               LUT4        A        In      -         8.296       -         
sender.bit_counter_RNO[2]               LUT4        Z        Out     0.661     8.957       -         
bit_counter_RNO[2]                      Net         -        -       1.507     -           1         
sender.bit_counter[2]                   FD1P3JZ     D        In      -         10.464      -         
=====================================================================================================
Total path delay (propagation time + setup) of 10.619 is 3.400(32.0%) logic and 7.219(68.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      9.027
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         8.872

    - Propagation time:                      10.392
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.521

    Number of logic level(s):                4
    Starting point:                          sender.baudrate_counter[3] / Q
    Ending point:                            sender.bit_counter[1] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                    Type        Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
sender.baudrate_counter[3]              FD1P3IZ     Q        Out     0.796     0.796       -         
baudrate_counter[3]                     Net         -        -       1.599     -           3         
sender.baudrate_counter_RNI48I41[0]     LUT4        B        In      -         2.395       -         
sender.baudrate_counter_RNI48I41[0]     LUT4        Z        Out     0.589     2.984       -         
un1_state7_i_o2_4                       Net         -        -       1.371     -           2         
sender.baudrate_counter_RNI7UVV1[1]     LUT4        D        In      -         4.355       -         
sender.baudrate_counter_RNI7UVV1[1]     LUT4        Z        Out     0.465     4.820       -         
N_103_0                                 Net         -        -       1.371     -           18        
sender.bit_counter_RNO_0[1]             LUT4        A        In      -         6.191       -         
sender.bit_counter_RNO_0[1]             LUT4        Z        Out     0.661     6.853       -         
bit_counter_7_i_out                     Net         -        -       1.371     -           1         
sender.bit_counter_RNO[1]               LUT4        A        In      -         8.224       -         
sender.bit_counter_RNO[1]               LUT4        Z        Out     0.661     8.885       -         
bit_counter_RNO[1]                      Net         -        -       1.507     -           1         
sender.bit_counter[1]                   FD1P3JZ     D        In      -         10.392      -         
=====================================================================================================
Total path delay (propagation time + setup) of 10.547 is 3.328(31.6%) logic and 7.219(68.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      9.027
    - Setup time:                            0.155
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         8.872

    - Propagation time:                      10.392
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -1.521

    Number of logic level(s):                4
    Starting point:                          sender.baudrate_counter[3] / Q
    Ending point:                            sender.bit_counter[0] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                    Type        Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
sender.baudrate_counter[3]              FD1P3IZ     Q        Out     0.796     0.796       -         
baudrate_counter[3]                     Net         -        -       1.599     -           3         
sender.baudrate_counter_RNI48I41[0]     LUT4        B        In      -         2.395       -         
sender.baudrate_counter_RNI48I41[0]     LUT4        Z        Out     0.589     2.984       -         
un1_state7_i_o2_4                       Net         -        -       1.371     -           2         
sender.baudrate_counter_RNI7UVV1[1]     LUT4        D        In      -         4.355       -         
sender.baudrate_counter_RNI7UVV1[1]     LUT4        Z        Out     0.465     4.820       -         
N_103_0                                 Net         -        -       1.371     -           18        
sender.state_RNIOEFQ2[0]                LUT4        A        In      -         6.191       -         
sender.state_RNIOEFQ2[0]                LUT4        Z        Out     0.661     6.853       -         
bit_counter_1_sqmuxa                    Net         -        -       1.371     -           3         
sender.bit_counter_RNO[0]               LUT4        A        In      -         8.224       -         
sender.bit_counter_RNO[0]               LUT4        Z        Out     0.661     8.885       -         
bit_counter                             Net         -        -       1.507     -           1         
sender.bit_counter[0]                   FD1P3DZ     D        In      -         10.392      -         
=====================================================================================================
Total path delay (propagation time + setup) of 10.547 is 3.328(31.6%) logic and 7.219(68.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)


Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB)

---------------------------------------
Resource Usage Report for top 

Mapping to part: ice40up5ksg48high-performance_1.2v
Cell usage:
CCU2_B          20 uses
FD1P3DZ         69 uses
FD1P3IZ         4 uses
FD1P3JZ         11 uses
GND             2 uses
RGB             1 use
VCC             2 uses
LUT4            102 uses

I/O ports: 6
I/O primitives: 3
IB             2 uses
OB             1 use

I/O Register bits:                  0
Register bits not including I/Os:   84 of 5280 (1%)
Total load per clock:
   top|clk: 1

@S |Mapping Summary:
Total  LUTs: 102 (1%)

Distribution of All Consumed LUTs = LUT4 
Distribution of All Consumed Luts 102 = 102 

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 27MB peak: 135MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Nov 19 20:44:08 2018

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