Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant (64-bit) 1.0.1.350.6
Mon Nov 19 22:19:24 2018
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2018 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt SerialTest_impl_1.tw1 SerialTest_impl_1.udb -gui
-----------------------------------------
Design: top
Family: iCE40UP
Device: iCE40UP5K
Package: SG48
Performance: High-Performance_1.2V
-----------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 DESIGN CHECKING
1.1 SDC Constraints
1.2 Combinational Loop
2 CLOCK SUMMARY
2.1 Clock clk
3 TIMING ANALYSIS SUMMARY
3.1 Overall (Setup and Hold)
3.1.1 Constraint Coverage
3.1.2 Timing Errors
3.1.3 Total Timing Score
3.2 Setup Summary Report
3.2.1 Setup Constraint Slack Summary
3.2.2 Setup Critical Endpoint Summary
3.3 Hold Summary Report
3.3.1 Hold Constraint Slack Summary
3.3.2 Hold Critical Endpoint Summary
3.4 Unconstrained Report
3.4.1 Unconstrained Start/End Points
3.4.2 Start/End Points Without Timing Constraints
4 DETAILED REPORT
4.1 Setup Detailed Report
4.1.1 Setup Path Details For Constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
4.2 Hold Detailed Report
4.2.1 Hold Path Details For Constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
=====================================================================
End of Table of Contents
=====================================================================
1 DESIGN CHECKING
1.1 SDC Constraints
create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
1.2 Combinational Loop
2 CLOCK SUMMARY
2.1 Clock "clk"
create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk | Target | 83.333 ns | 12.000 MHz
| Actual (all paths) | 23.423 ns | 42.693 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
3 TIMING ANALYSIS SUMMARY
3.1 Overall (Setup and Hold)
3.1.1 Constraint Coverage
Constraint Coverage: 99.0836%
3.1.2 Timing Errors
Timing Errors: 0 endpoints (setup), 0 endpoints (hold)
3.1.3 Total Timing Score
Total Negative Slack: 0.000 ns (setup), 0.000 ns (hold)
3.2 Setup Summary Report
3.2.1 Setup Constraint Slack Summary
-------------------------------------------------------------------------------------------------------------------------------------------
| | | | Actual (flop to flop) | |
SDC Constraint | Target | Slack | Levels | Period | Frequency | Items Scored | Timing Error
-------------------------------------------------------------------------------------------------------------------------------------------
| | | | | | |
create_clock -name {clk} -period 83.333
3333333333 [get_ports clk] | 83.333 ns | 59.910 ns | 24 | 23.423 ns | 42.693 MHz | 255 | 0
-------------------------------------------------------------------------------------------------------------------------------------------
3.2.2 Setup Critical Endpoint Summary
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
counter_451__i22/D | 59.910 ns
counter_451__i21/D | 60.826 ns
counter_451__i20/D | 61.742 ns
counter_451__i19/D | 62.658 ns
counter_451__i18/D | 63.574 ns
counter_451__i17/D | 64.490 ns
counter_451__i16/D | 65.406 ns
counter_451__i15/D | 66.322 ns
counter_451__i14/D | 67.238 ns
ram_ad__i13/D | 67.889 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
3.3 Hold Summary Report
3.3.1 Hold Constraint Slack Summary
-------------------------------------------------------------------------------------------------------------------------------------------
| | | | Actual (flop to flop) | |
SDC Constraint | Target | Slack | Levels | Period | Frequency | Items Scored | Timing Error
-------------------------------------------------------------------------------------------------------------------------------------------
| | | | | | |
create_clock -name {clk} -period 83.333
3333333333 [get_ports clk] | 0.000 ns | 1.753 ns | 1 | ---- | ---- | 255 | 0
-------------------------------------------------------------------------------------------------------------------------------------------
3.3.2 Hold Critical Endpoint Summary
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
ram/WREN | 1.753 ns
ram/DATAIN15 | 1.821 ns
ram/DATAIN14 | 1.821 ns
ram/DATAIN13 | 1.821 ns
ram/DATAIN12 | 1.821 ns
ram/DATAIN11 | 1.821 ns
ram/DATAIN10 | 1.821 ns
ram/DATAIN9 | 1.821 ns
ram/DATAIN8 | 1.821 ns
ram/DATAIN7 | 1.821 ns
-------------------------------------------------------
|
Hold # of endpoints with negative slack: | 0
|
-------------------------------------------------------
3.4 Unconstrained Report
3.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
-------------------------------------------------------------------
Listing 10 Start Points | Type
-------------------------------------------------------------------
sender/tx_56/PADDO | No required time
ram/DATAOUT15 | No arrival or required
ram/DATAOUT14 | No arrival or required
ram/DATAOUT13 | No arrival or required
ram/DATAOUT12 | No arrival or required
ram/DATAOUT11 | No arrival or required
ram/DATAOUT10 | No arrival or required
ram/DATAOUT9 | No arrival or required
ram/DATAOUT8 | No arrival or required
ram/DATAOUT7 | No arrival or required
-------------------------------------------------------------------
|
Number of unconstrained timing start po |
ints | 18
|
-------------------------------------------------------------------
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 1 End Points | Type
-------------------------------------------------------------------
receiver/rx_latch_55/PADDI | No arrival time
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 1
|
-------------------------------------------------------------------
3.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 5 Start or End Points | Type
-------------------------------------------------------------------
txd | input
led_blue | output
led_green | output
led_red | output
rxd | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 5
|
-------------------------------------------------------------------
Registers without clock definition
Define the clock for these registers.
--------------------------------------------------
There is no instance satisfying reporting criteria
4 DETAILED REPORT
4.1 Setup Detailed Report
4.1.1 Setup path details for constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
----------------------------------------------------------------------
255 endpoints scored, 0 timing errors detected.
Minimum Pulse Width Report
--------------------------
MPW Cell : SRAM
MPW Pin : CLOCK
MPW Period : 0.418 ns
Clock Period : 83.3333 ns
Period margin : 82.9153 ns (Passed)
--------------------------
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i22/D
Source Clock : clk
Destination Clock: clk
Logic Level : 24
Delay Ratio : 65.3% (route), 34.7% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 59.910 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 23.224
------------------------------------- ------
End-of-path arrival time( ns ) 25.236
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q SLICE CLK_TO_Q1_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.638 4.041 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
SLICE C1_TO_COUT1_DELAY 0.344 4.385 2
n2209 NET DELAY 0.638 5.023 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 5.301 2
n3443 NET DELAY 0.638 5.939 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 6.217 2
n2211 NET DELAY 0.638 6.855 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 7.133 2
n3446 NET DELAY 0.638 7.771 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 8.049 2
n2213 NET DELAY 0.638 8.687 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 8.965 2
n3449 NET DELAY 0.638 9.603 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 9.881 2
n2215 NET DELAY 0.638 10.519 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 10.797 2
n3452 NET DELAY 0.638 11.435 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 11.713 2
n2217 NET DELAY 0.638 12.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 12.629 2
n3455 NET DELAY 0.638 13.267 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 13.545 2
n2219 NET DELAY 0.638 14.183 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 14.461 2
n3458 NET DELAY 0.638 15.099 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 15.377 2
n2221 NET DELAY 0.638 16.015 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 16.293 2
n3461 NET DELAY 0.638 16.931 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 17.209 2
n2223 NET DELAY 0.638 17.847 1
counter_451_add_4_17/CI0->counter_451_add_4_17/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 18.125 2
n3464 NET DELAY 0.638 18.763 1
counter_451_add_4_17/CI1->counter_451_add_4_17/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 19.041 2
n2225 NET DELAY 0.638 19.679 1
counter_451_add_4_19/CI0->counter_451_add_4_19/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 19.957 2
n3467 NET DELAY 0.638 20.595 1
counter_451_add_4_19/CI1->counter_451_add_4_19/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 20.873 2
n2227 NET DELAY 0.638 21.511 1
counter_451_add_4_21/CI0->counter_451_add_4_21/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 21.789 2
n3470 NET DELAY 0.638 22.427 1
counter_451_add_4_21/CI1->counter_451_add_4_21/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 22.705 2
n2229 NET DELAY 0.638 23.343 1
counter_451_add_4_23/CI0->counter_451_add_4_23/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 23.621 2
n3473 NET DELAY 0.638 24.259 1
counter_451_add_4_23/D1->counter_451_add_4_23/S1
SLICE D1_TO_F1_DELAY 0.477 24.736 1
n98 NET DELAY 0.500 25.236 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i21/D
Source Clock : clk
Destination Clock: clk
Logic Level : 23
Delay Ratio : 65.2% (route), 34.8% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 60.826 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 22.308
------------------------------------- ------
End-of-path arrival time( ns ) 24.320
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q SLICE CLK_TO_Q1_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.638 4.041 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
SLICE C1_TO_COUT1_DELAY 0.344 4.385 2
n2209 NET DELAY 0.638 5.023 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 5.301 2
n3443 NET DELAY 0.638 5.939 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 6.217 2
n2211 NET DELAY 0.638 6.855 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 7.133 2
n3446 NET DELAY 0.638 7.771 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 8.049 2
n2213 NET DELAY 0.638 8.687 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 8.965 2
n3449 NET DELAY 0.638 9.603 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 9.881 2
n2215 NET DELAY 0.638 10.519 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 10.797 2
n3452 NET DELAY 0.638 11.435 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 11.713 2
n2217 NET DELAY 0.638 12.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 12.629 2
n3455 NET DELAY 0.638 13.267 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 13.545 2
n2219 NET DELAY 0.638 14.183 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 14.461 2
n3458 NET DELAY 0.638 15.099 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 15.377 2
n2221 NET DELAY 0.638 16.015 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 16.293 2
n3461 NET DELAY 0.638 16.931 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 17.209 2
n2223 NET DELAY 0.638 17.847 1
counter_451_add_4_17/CI0->counter_451_add_4_17/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 18.125 2
n3464 NET DELAY 0.638 18.763 1
counter_451_add_4_17/CI1->counter_451_add_4_17/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 19.041 2
n2225 NET DELAY 0.638 19.679 1
counter_451_add_4_19/CI0->counter_451_add_4_19/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 19.957 2
n3467 NET DELAY 0.638 20.595 1
counter_451_add_4_19/CI1->counter_451_add_4_19/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 20.873 2
n2227 NET DELAY 0.638 21.511 1
counter_451_add_4_21/CI0->counter_451_add_4_21/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 21.789 2
n3470 NET DELAY 0.638 22.427 1
counter_451_add_4_21/CI1->counter_451_add_4_21/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 22.705 2
n2229 NET DELAY 0.638 23.343 1
counter_451_add_4_23/D0->counter_451_add_4_23/S0
SLICE D0_TO_F0_DELAY 0.477 23.820 1
n99 NET DELAY 0.500 24.320 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i20/D
Source Clock : clk
Destination Clock: clk
Logic Level : 22
Delay Ratio : 65.0% (route), 35.0% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 61.742 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 21.392
------------------------------------- ------
End-of-path arrival time( ns ) 23.404
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q SLICE CLK_TO_Q1_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.638 4.041 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
SLICE C1_TO_COUT1_DELAY 0.344 4.385 2
n2209 NET DELAY 0.638 5.023 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 5.301 2
n3443 NET DELAY 0.638 5.939 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 6.217 2
n2211 NET DELAY 0.638 6.855 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 7.133 2
n3446 NET DELAY 0.638 7.771 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 8.049 2
n2213 NET DELAY 0.638 8.687 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 8.965 2
n3449 NET DELAY 0.638 9.603 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 9.881 2
n2215 NET DELAY 0.638 10.519 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 10.797 2
n3452 NET DELAY 0.638 11.435 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 11.713 2
n2217 NET DELAY 0.638 12.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 12.629 2
n3455 NET DELAY 0.638 13.267 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 13.545 2
n2219 NET DELAY 0.638 14.183 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 14.461 2
n3458 NET DELAY 0.638 15.099 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 15.377 2
n2221 NET DELAY 0.638 16.015 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 16.293 2
n3461 NET DELAY 0.638 16.931 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 17.209 2
n2223 NET DELAY 0.638 17.847 1
counter_451_add_4_17/CI0->counter_451_add_4_17/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 18.125 2
n3464 NET DELAY 0.638 18.763 1
counter_451_add_4_17/CI1->counter_451_add_4_17/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 19.041 2
n2225 NET DELAY 0.638 19.679 1
counter_451_add_4_19/CI0->counter_451_add_4_19/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 19.957 2
n3467 NET DELAY 0.638 20.595 1
counter_451_add_4_19/CI1->counter_451_add_4_19/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 20.873 2
n2227 NET DELAY 0.638 21.511 1
counter_451_add_4_21/CI0->counter_451_add_4_21/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 21.789 2
n3470 NET DELAY 0.638 22.427 1
counter_451_add_4_21/D1->counter_451_add_4_21/S1
SLICE D1_TO_F1_DELAY 0.477 22.904 1
n100 NET DELAY 0.500 23.404 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i19/D
Source Clock : clk
Destination Clock: clk
Logic Level : 21
Delay Ratio : 64.8% (route), 35.2% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 62.658 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 20.476
------------------------------------- ------
End-of-path arrival time( ns ) 22.488
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q SLICE CLK_TO_Q1_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.638 4.041 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
SLICE C1_TO_COUT1_DELAY 0.344 4.385 2
n2209 NET DELAY 0.638 5.023 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 5.301 2
n3443 NET DELAY 0.638 5.939 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 6.217 2
n2211 NET DELAY 0.638 6.855 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 7.133 2
n3446 NET DELAY 0.638 7.771 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 8.049 2
n2213 NET DELAY 0.638 8.687 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 8.965 2
n3449 NET DELAY 0.638 9.603 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 9.881 2
n2215 NET DELAY 0.638 10.519 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 10.797 2
n3452 NET DELAY 0.638 11.435 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 11.713 2
n2217 NET DELAY 0.638 12.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 12.629 2
n3455 NET DELAY 0.638 13.267 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 13.545 2
n2219 NET DELAY 0.638 14.183 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 14.461 2
n3458 NET DELAY 0.638 15.099 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 15.377 2
n2221 NET DELAY 0.638 16.015 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 16.293 2
n3461 NET DELAY 0.638 16.931 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 17.209 2
n2223 NET DELAY 0.638 17.847 1
counter_451_add_4_17/CI0->counter_451_add_4_17/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 18.125 2
n3464 NET DELAY 0.638 18.763 1
counter_451_add_4_17/CI1->counter_451_add_4_17/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 19.041 2
n2225 NET DELAY 0.638 19.679 1
counter_451_add_4_19/CI0->counter_451_add_4_19/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 19.957 2
n3467 NET DELAY 0.638 20.595 1
counter_451_add_4_19/CI1->counter_451_add_4_19/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 20.873 2
n2227 NET DELAY 0.638 21.511 1
counter_451_add_4_21/D0->counter_451_add_4_21/S0
SLICE D0_TO_F0_DELAY 0.477 21.988 1
n101 NET DELAY 0.500 22.488 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i18/D
Source Clock : clk
Destination Clock: clk
Logic Level : 20
Delay Ratio : 64.5% (route), 35.5% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 63.574 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 19.560
------------------------------------- ------
End-of-path arrival time( ns ) 21.572
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q SLICE CLK_TO_Q1_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.638 4.041 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
SLICE C1_TO_COUT1_DELAY 0.344 4.385 2
n2209 NET DELAY 0.638 5.023 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 5.301 2
n3443 NET DELAY 0.638 5.939 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 6.217 2
n2211 NET DELAY 0.638 6.855 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 7.133 2
n3446 NET DELAY 0.638 7.771 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 8.049 2
n2213 NET DELAY 0.638 8.687 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 8.965 2
n3449 NET DELAY 0.638 9.603 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 9.881 2
n2215 NET DELAY 0.638 10.519 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 10.797 2
n3452 NET DELAY 0.638 11.435 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 11.713 2
n2217 NET DELAY 0.638 12.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 12.629 2
n3455 NET DELAY 0.638 13.267 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 13.545 2
n2219 NET DELAY 0.638 14.183 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 14.461 2
n3458 NET DELAY 0.638 15.099 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 15.377 2
n2221 NET DELAY 0.638 16.015 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 16.293 2
n3461 NET DELAY 0.638 16.931 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 17.209 2
n2223 NET DELAY 0.638 17.847 1
counter_451_add_4_17/CI0->counter_451_add_4_17/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 18.125 2
n3464 NET DELAY 0.638 18.763 1
counter_451_add_4_17/CI1->counter_451_add_4_17/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 19.041 2
n2225 NET DELAY 0.638 19.679 1
counter_451_add_4_19/CI0->counter_451_add_4_19/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 19.957 2
n3467 NET DELAY 0.638 20.595 1
counter_451_add_4_19/D1->counter_451_add_4_19/S1
SLICE D1_TO_F1_DELAY 0.477 21.072 1
n102 NET DELAY 0.500 21.572 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i17/D
Source Clock : clk
Destination Clock: clk
Logic Level : 19
Delay Ratio : 64.3% (route), 35.7% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 64.490 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 18.644
------------------------------------- ------
End-of-path arrival time( ns ) 20.656
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q SLICE CLK_TO_Q1_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.638 4.041 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
SLICE C1_TO_COUT1_DELAY 0.344 4.385 2
n2209 NET DELAY 0.638 5.023 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 5.301 2
n3443 NET DELAY 0.638 5.939 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 6.217 2
n2211 NET DELAY 0.638 6.855 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 7.133 2
n3446 NET DELAY 0.638 7.771 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 8.049 2
n2213 NET DELAY 0.638 8.687 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 8.965 2
n3449 NET DELAY 0.638 9.603 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 9.881 2
n2215 NET DELAY 0.638 10.519 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 10.797 2
n3452 NET DELAY 0.638 11.435 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 11.713 2
n2217 NET DELAY 0.638 12.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 12.629 2
n3455 NET DELAY 0.638 13.267 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 13.545 2
n2219 NET DELAY 0.638 14.183 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 14.461 2
n3458 NET DELAY 0.638 15.099 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 15.377 2
n2221 NET DELAY 0.638 16.015 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 16.293 2
n3461 NET DELAY 0.638 16.931 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 17.209 2
n2223 NET DELAY 0.638 17.847 1
counter_451_add_4_17/CI0->counter_451_add_4_17/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 18.125 2
n3464 NET DELAY 0.638 18.763 1
counter_451_add_4_17/CI1->counter_451_add_4_17/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 19.041 2
n2225 NET DELAY 0.638 19.679 1
counter_451_add_4_19/D0->counter_451_add_4_19/S0
SLICE D0_TO_F0_DELAY 0.477 20.156 1
n103 NET DELAY 0.500 20.656 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i16/D
Source Clock : clk
Destination Clock: clk
Logic Level : 18
Delay Ratio : 64.0% (route), 36.0% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 65.406 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 17.728
------------------------------------- ------
End-of-path arrival time( ns ) 19.740
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q SLICE CLK_TO_Q1_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.638 4.041 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
SLICE C1_TO_COUT1_DELAY 0.344 4.385 2
n2209 NET DELAY 0.638 5.023 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 5.301 2
n3443 NET DELAY 0.638 5.939 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 6.217 2
n2211 NET DELAY 0.638 6.855 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 7.133 2
n3446 NET DELAY 0.638 7.771 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 8.049 2
n2213 NET DELAY 0.638 8.687 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 8.965 2
n3449 NET DELAY 0.638 9.603 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 9.881 2
n2215 NET DELAY 0.638 10.519 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 10.797 2
n3452 NET DELAY 0.638 11.435 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 11.713 2
n2217 NET DELAY 0.638 12.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 12.629 2
n3455 NET DELAY 0.638 13.267 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 13.545 2
n2219 NET DELAY 0.638 14.183 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 14.461 2
n3458 NET DELAY 0.638 15.099 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 15.377 2
n2221 NET DELAY 0.638 16.015 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 16.293 2
n3461 NET DELAY 0.638 16.931 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 17.209 2
n2223 NET DELAY 0.638 17.847 1
counter_451_add_4_17/CI0->counter_451_add_4_17/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 18.125 2
n3464 NET DELAY 0.638 18.763 1
counter_451_add_4_17/D1->counter_451_add_4_17/S1
SLICE D1_TO_F1_DELAY 0.477 19.240 1
n104 NET DELAY 0.500 19.740 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i15/D
Source Clock : clk
Destination Clock: clk
Logic Level : 17
Delay Ratio : 63.7% (route), 36.3% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 66.322 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 16.812
------------------------------------- ------
End-of-path arrival time( ns ) 18.824
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q SLICE CLK_TO_Q1_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.638 4.041 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
SLICE C1_TO_COUT1_DELAY 0.344 4.385 2
n2209 NET DELAY 0.638 5.023 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 5.301 2
n3443 NET DELAY 0.638 5.939 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 6.217 2
n2211 NET DELAY 0.638 6.855 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 7.133 2
n3446 NET DELAY 0.638 7.771 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 8.049 2
n2213 NET DELAY 0.638 8.687 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 8.965 2
n3449 NET DELAY 0.638 9.603 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 9.881 2
n2215 NET DELAY 0.638 10.519 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 10.797 2
n3452 NET DELAY 0.638 11.435 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 11.713 2
n2217 NET DELAY 0.638 12.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 12.629 2
n3455 NET DELAY 0.638 13.267 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 13.545 2
n2219 NET DELAY 0.638 14.183 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 14.461 2
n3458 NET DELAY 0.638 15.099 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 15.377 2
n2221 NET DELAY 0.638 16.015 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 16.293 2
n3461 NET DELAY 0.638 16.931 1
counter_451_add_4_15/CI1->counter_451_add_4_15/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 17.209 2
n2223 NET DELAY 0.638 17.847 1
counter_451_add_4_17/D0->counter_451_add_4_17/S0
SLICE D0_TO_F0_DELAY 0.477 18.324 1
n105 NET DELAY 0.500 18.824 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : counter_451__i0/Q
Path End : counter_451__i14/D
Source Clock : clk
Destination Clock: clk
Logic Level : 16
Delay Ratio : 63.3% (route), 36.7% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 67.238 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 15.896
------------------------------------- ------
End-of-path arrival time( ns ) 17.908
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------------- ----- ------------ ------
counter_451__i0/CK->counter_451__i0/Q SLICE CLK_TO_Q1_DELAY 1.391 3.403 2
counter[0] NET DELAY 0.638 4.041 1
counter_451_add_4_1/C1->counter_451_add_4_1/CO1
SLICE C1_TO_COUT1_DELAY 0.344 4.385 2
n2209 NET DELAY 0.638 5.023 1
counter_451_add_4_3/CI0->counter_451_add_4_3/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 5.301 2
n3443 NET DELAY 0.638 5.939 1
counter_451_add_4_3/CI1->counter_451_add_4_3/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 6.217 2
n2211 NET DELAY 0.638 6.855 1
counter_451_add_4_5/CI0->counter_451_add_4_5/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 7.133 2
n3446 NET DELAY 0.638 7.771 1
counter_451_add_4_5/CI1->counter_451_add_4_5/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 8.049 2
n2213 NET DELAY 0.638 8.687 1
counter_451_add_4_7/CI0->counter_451_add_4_7/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 8.965 2
n3449 NET DELAY 0.638 9.603 1
counter_451_add_4_7/CI1->counter_451_add_4_7/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 9.881 2
n2215 NET DELAY 0.638 10.519 1
counter_451_add_4_9/CI0->counter_451_add_4_9/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 10.797 2
n3452 NET DELAY 0.638 11.435 1
counter_451_add_4_9/CI1->counter_451_add_4_9/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 11.713 2
n2217 NET DELAY 0.638 12.351 1
counter_451_add_4_11/CI0->counter_451_add_4_11/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 12.629 2
n3455 NET DELAY 0.638 13.267 1
counter_451_add_4_11/CI1->counter_451_add_4_11/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 13.545 2
n2219 NET DELAY 0.638 14.183 1
counter_451_add_4_13/CI0->counter_451_add_4_13/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 14.461 2
n3458 NET DELAY 0.638 15.099 1
counter_451_add_4_13/CI1->counter_451_add_4_13/CO1
SLICE CIN1_TO_COUT1_DELAY 0.278 15.377 2
n2221 NET DELAY 0.638 16.015 1
counter_451_add_4_15/CI0->counter_451_add_4_15/CO0
SLICE CIN0_TO_COUT0_DELAY 0.278 16.293 2
n3461 NET DELAY 0.638 16.931 1
counter_451_add_4_15/D1->counter_451_add_4_15/S1
SLICE D1_TO_F1_DELAY 0.477 17.408 1
n106 NET DELAY 0.500 17.908 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_ad__i0/Q
Path End : ram_ad__i13/D
Source Clock : clk
Destination Clock: clk
Logic Level : 15
Delay Ratio : 63.5% (route), 36.5% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 83.333 ns
Path Slack : 67.889 ns (Passed)
Destination Clock Arrival Time (clk:R#2) 83.333
+ Destination Clock Source Latency 0.000
- Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
- Setup Time 0.199
------------------------------------------ -------
End-of-path required time( ns ) 85.146
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 15.245
------------------------------------- ------
End-of-path arrival time( ns ) 17.257
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- ------------------- ----- ------------ ------
ram_ad__i0/CK->ram_ad__i0/Q SLICE CLK_TO_Q1_DELAY 1.391 3.403 7
ram_ad[0] NET DELAY 0.889 4.292 1
add_20_add_4_1/B1->add_20_add_4_1/CO1 SLICE B1_TO_COUT1_DELAY 0.358 4.650 2
n2186 NET DELAY 0.638 5.288 1
add_20_add_4_3/CI0->add_20_add_4_3/CO0 SLICE CIN0_TO_COUT0_DELAY 0.278 5.566 2
n3491 NET DELAY 0.638 6.204 1
add_20_add_4_3/CI1->add_20_add_4_3/CO1 SLICE CIN1_TO_COUT1_DELAY 0.278 6.482 2
n2188 NET DELAY 0.638 7.120 1
add_20_add_4_5/CI0->add_20_add_4_5/CO0 SLICE CIN0_TO_COUT0_DELAY 0.278 7.398 2
n3494 NET DELAY 0.638 8.036 1
add_20_add_4_5/CI1->add_20_add_4_5/CO1 SLICE CIN1_TO_COUT1_DELAY 0.278 8.314 2
n2190 NET DELAY 0.638 8.952 1
add_20_add_4_7/CI0->add_20_add_4_7/CO0 SLICE CIN0_TO_COUT0_DELAY 0.278 9.230 2
n3497 NET DELAY 0.638 9.868 1
add_20_add_4_7/CI1->add_20_add_4_7/CO1 SLICE CIN1_TO_COUT1_DELAY 0.278 10.146 2
n2192 NET DELAY 0.638 10.784 1
add_20_add_4_9/CI0->add_20_add_4_9/CO0 SLICE CIN0_TO_COUT0_DELAY 0.278 11.062 2
n3500 NET DELAY 0.638 11.700 1
add_20_add_4_9/CI1->add_20_add_4_9/CO1 SLICE CIN1_TO_COUT1_DELAY 0.278 11.978 2
n2194 NET DELAY 0.638 12.616 1
add_20_add_4_11/CI0->add_20_add_4_11/CO0 SLICE CIN0_TO_COUT0_DELAY 0.278 12.894 2
n3503 NET DELAY 0.638 13.532 1
add_20_add_4_11/CI1->add_20_add_4_11/CO1 SLICE CIN1_TO_COUT1_DELAY 0.278 13.810 2
n2196 NET DELAY 0.638 14.448 1
add_20_add_4_13/CI0->add_20_add_4_13/CO0 SLICE CIN0_TO_COUT0_DELAY 0.278 14.726 2
n3506 NET DELAY 0.638 15.364 1
add_20_add_4_13/CI1->add_20_add_4_13/CO1 SLICE CIN1_TO_COUT1_DELAY 0.278 15.642 2
n2198 NET DELAY 0.638 16.280 1
add_20_add_4_15/D0->add_20_add_4_15/S0 SLICE D0_TO_F0_DELAY 0.477 16.757 1
n32 NET DELAY 0.500 17.257 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
4.2 Hold Detailed Report
4.2.1 Hold path details for constraint: create_clock -name {clk} -period 83.3333333333333 [get_ports clk]
----------------------------------------------------------------------
255 endpoints scored, 0 timing errors detected.
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_we_104/Q
Path End : ram/WREN
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 26.4% (route), 73.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.753 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.138
------------------------------------------ -------
End-of-path required time( ns ) 2.150
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 1.891
------------------------------------- -----
End-of-path arrival time( ns ) 3.903
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- --------------- ----- ------------ ------
ram_we_104/CK->ram_we_104/Q SLICE CLK_TO_Q0_DELAY 1.391 3.403 1
ram_we NET DELAY 0.500 3.903 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i12/Q
Path End : ram/DATAIN12
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.821 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.029
------------------------------------- -----
End-of-path arrival time( ns ) 4.041
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- --------------- ----- ------------ ------
ram_di_i0_i12/CK->ram_di_i0_i12/Q SLICE CLK_TO_Q0_DELAY 1.391 3.403 2
ram_di[12] NET DELAY 0.638 4.041 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i14/Q
Path End : ram/DATAIN14
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.821 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.029
------------------------------------- -----
End-of-path arrival time( ns ) 4.041
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- --------------- ----- ------------ ------
ram_di_i0_i14/CK->ram_di_i0_i14/Q SLICE CLK_TO_Q0_DELAY 1.391 3.403 2
ram_di[14] NET DELAY 0.638 4.041 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i15/Q
Path End : ram/DATAIN15
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.821 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.029
------------------------------------- -----
End-of-path arrival time( ns ) 4.041
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- --------------- ----- ------------ ------
ram_di_i0_i15/CK->ram_di_i0_i15/Q SLICE CLK_TO_Q0_DELAY 1.391 3.403 2
ram_di[15] NET DELAY 0.638 4.041 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i13/Q
Path End : ram/DATAIN13
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.821 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.029
------------------------------------- -----
End-of-path arrival time( ns ) 4.041
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- --------------- ----- ------------ ------
ram_di_i0_i13/CK->ram_di_i0_i13/Q SLICE CLK_TO_Q0_DELAY 1.391 3.403 2
ram_di[13] NET DELAY 0.638 4.041 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i0/Q
Path End : ram/DATAIN0
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.821 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.029
------------------------------------- -----
End-of-path arrival time( ns ) 4.041
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- --------------- ----- ------------ ------
ram_di_i0_i0/CK->ram_di_i0_i0/Q SLICE CLK_TO_Q0_DELAY 1.391 3.403 2
ram_di[0] NET DELAY 0.638 4.041 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i1/Q
Path End : ram/DATAIN1
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.821 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.029
------------------------------------- -----
End-of-path arrival time( ns ) 4.041
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- --------------- ----- ------------ ------
ram_di_i0_i1/CK->ram_di_i0_i1/Q SLICE CLK_TO_Q0_DELAY 1.391 3.403 2
ram_di[1] NET DELAY 0.638 4.041 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i2/Q
Path End : ram/DATAIN2
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.821 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.029
------------------------------------- -----
End-of-path arrival time( ns ) 4.041
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- --------------- ----- ------------ ------
ram_di_i0_i2/CK->ram_di_i0_i2/Q SLICE CLK_TO_Q0_DELAY 1.391 3.403 2
ram_di[2] NET DELAY 0.638 4.041 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i3/Q
Path End : ram/DATAIN3
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.821 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.029
------------------------------------- -----
End-of-path arrival time( ns ) 4.041
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- --------------- ----- ------------ ------
ram_di_i0_i3/CK->ram_di_i0_i3/Q SLICE CLK_TO_Q0_DELAY 1.391 3.403 2
ram_di[3] NET DELAY 0.638 4.041 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
++++Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : ram_di_i0_i4/Q
Path End : ram/DATAIN4
Source Clock : clk
Destination Clock: clk
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 1.821 ns (Passed)
Destination Clock Arrival Time (clk:R#1) 0.000
+ Destination Clock Source Latency 0.000
+ Destination Clock Uncertainty 0.000
+ Destination Clock Path Delay 2.012
+ Hold Time -0.208
------------------------------------------ -------
End-of-path required time( ns ) 2.220
Source Clock Arrival Time (clk:R#1) 0.000
+ Source Clock Source Latency 0.000
+ Source Clock Path Delay 2.012
+ Data Path Delay 2.029
------------------------------------- -----
End-of-path arrival time( ns ) 4.041
Source Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
Data path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- --------------- ----- ------------ ------
ram_di_i0_i4/CK->ram_di_i0_i4/Q SLICE CLK_TO_Q0_DELAY 1.391 3.403 2
ram_di[4] NET DELAY 0.638 4.041 1
Destination Clock Path
Name Cell/Site Name Delay Name Delay Arrival Time Fanout
---------------------------------------- -------------- -------------------- ----- ------------ ------
clk top CLOCK LATENCY 0.000 0.000 1
clk NET DELAY 0.000 0.000 1
clk_pad.bb_inst/B->clk_pad.bb_inst/O PIO IOPAD_TO_PADDI_DELAY 0.510 0.510 106
clk_c NET DELAY 1.502 2.012 1
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++