bandwidth_mode == BANDWIDTH_MODE_AUTO
base_address == 16'b0000000000000000000000000000000000000000000000000000000000000000
cascade_mode == CASCADE_MODE_STANDALONE
clk_switch_auto_en == CLK_SWITCH_AUTO_EN_FALSE
clk_switch_manual_en == CLK_SWITCH_MANUAL_EN_FALSE
compensation_clk_source == COMPENSATION_CLK_SOURCE_UNUSED
compensation_mode == COMPENSATION_MODE_DIRECT
fb_clk_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
fb_clk_fractional_div_den == 32'b0000000000000000000000000000000000000000000000000000000000000001
fb_clk_fractional_div_num == 32'b0000000000000000000000000000000000000000000000000000000000000001
fb_clk_fractional_div_value == 32'b0000000000000000000000000000000000000000000000000000000000000001
fb_clk_m_div == 9'b0000000000000000000000000000000000000000000000000000000000001110
out_clk_0_c_div == 9'b0000000000000000000000000000000000000000000000000000000000000010
out_clk_0_core_en == OUT_CLK_0_CORE_EN_TRUE
out_clk_0_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_0_dutycycle_den == 32'b0000000000000000000000000000000000000000000000000000000000000100
out_clk_0_dutycycle_num == 32'b0000000000000000000000000000000000000000000000000000000000000010
out_clk_0_dutycycle_percent == 32'b0000000000000000000000000000000000000000000000000000000000110010
out_clk_0_freq == 36'b0000000000000000000000000000000000101001101110010010011100000000
out_clk_0_phase_ps == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_0_phase_shifts == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_1_c_div == 9'b0000000000000000000000000000000000000000000000000000000111111110
out_clk_1_core_en == OUT_CLK_1_CORE_EN_FALSE
out_clk_1_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_1_dutycycle_den == 32'b0000000000000000000000000000000000000000000000000000001111111100
out_clk_1_dutycycle_num == 32'b0000000000000000000000000000000000000000000000000000000111111110
out_clk_1_dutycycle_percent == 32'b0000000000000000000000000000000000000000000000000000000000110010
out_clk_1_freq == 36'b0000000000000000000000000000000000000000001010011110001100001010
out_clk_1_phase_ps == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_1_phase_shifts == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_2_c_div == 9'b0000000000000000000000000000000000000000000000000000000000000001
out_clk_2_core_en == OUT_CLK_2_CORE_EN_FALSE
out_clk_2_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_2_dutycycle_den == 32'b0000000000000000000000000000000000000000000000000000000000000100
out_clk_2_dutycycle_num == 32'b0000000000000000000000000000000000000000000000000000000000000010
out_clk_2_dutycycle_percent == 32'b0000000000000000000000000000000000000000000000000000000000110010
out_clk_2_freq == 36'b0000000000000000000000000000000001010011011100100100111000000000
out_clk_2_phase_ps == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_2_phase_shifts == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_3_c_div == 9'b0000000000000000000000000000000000000000000000000000000000000001
out_clk_3_core_en == OUT_CLK_3_CORE_EN_FALSE
out_clk_3_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_3_dutycycle_den == 32'b0000000000000000000000000000000000000000000000000000000000000100
out_clk_3_dutycycle_num == 32'b0000000000000000000000000000000000000000000000000000000000000010
out_clk_3_dutycycle_percent == 32'b0000000000000000000000000000000000000000000000000000000000110010
out_clk_3_freq == 36'b0000000000000000000000000000000001010011011100100100111000000000
out_clk_3_phase_ps == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_3_phase_shifts == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_4_c_div == 9'b0000000000000000000000000000000000000000000000000000000000000001
out_clk_4_core_en == OUT_CLK_4_CORE_EN_FALSE
out_clk_4_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_4_dutycycle_den == 32'b0000000000000000000000000000000000000000000000000000000000000100
out_clk_4_dutycycle_num == 32'b0000000000000000000000000000000000000000000000000000000000000010
out_clk_4_dutycycle_percent == 32'b0000000000000000000000000000000000000000000000000000000000110010
out_clk_4_freq == 36'b0000000000000000000000000000000001010011011100100100111000000000
out_clk_4_phase_ps == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_4_phase_shifts == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_5_c_div == 9'b0000000000000000000000000000000000000000000000000000000000000001
out_clk_5_core_en == OUT_CLK_5_CORE_EN_FALSE
out_clk_5_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_5_dutycycle_den == 32'b0000000000000000000000000000000000000000000000000000000000000100
out_clk_5_dutycycle_num == 32'b0000000000000000000000000000000000000000000000000000000000000010
out_clk_5_dutycycle_percent == 32'b0000000000000000000000000000000000000000000000000000000000110010
out_clk_5_freq == 36'b0000000000000000000000000000000001010011011100100100111000000000
out_clk_5_phase_ps == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_5_phase_shifts == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_6_c_div == 9'b0000000000000000000000000000000000000000000000000000000000000001
out_clk_6_core_en == OUT_CLK_6_CORE_EN_FALSE
out_clk_6_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_6_dutycycle_den == 32'b0000000000000000000000000000000000000000000000000000000000000100
out_clk_6_dutycycle_num == 32'b0000000000000000000000000000000000000000000000000000000000000010
out_clk_6_dutycycle_percent == 32'b0000000000000000000000000000000000000000000000000000000000110010
out_clk_6_freq == 36'b0000000000000000000000000000000001010011011100100100111000000000
out_clk_6_phase_ps == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_6_phase_shifts == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_cascading_source == OUT_CLK_CASCADING_SOURCE_UNUSED
out_clk_external_0_source == OUT_CLK_EXTERNAL_0_SOURCE_UNUSED
out_clk_external_1_source == OUT_CLK_EXTERNAL_1_SOURCE_UNUSED
out_clk_periph_0_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_periph_0_en == OUT_CLK_PERIPH_0_EN_FALSE
out_clk_periph_1_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
out_clk_periph_1_en == OUT_CLK_PERIPH_1_EN_FALSE
pfd_clk_freq == 32'b0000000000000000000000000000000000000101111101011110000100000000
powerdown_mode == FALSE
protocol_mode == PROTOCOL_MODE_UIB
ref_clk_0_freq == 32'b0000000000000000000000000000000000000101111101011110000100000000
ref_clk_1_freq == 32'b0000000000000000000000000000000000000000000000000000000000000000
ref_clk_delay == 32'b0000000000000000000000000000000000000000000000000000000000000000
ref_clk_n_div == 9'b0000000000000000000000000000000000000000000000000000000000000001
self_reset_en == SELF_RESET_EN_FALSE
set_dutycycle == SET_DUTYCYCLE_FRACTION
set_fractional == SET_FRACTIONAL_FRACTION
set_freq == SET_FREQ_DIVISION_VERIFY
set_phase == SET_PHASE_NUM_SHIFTS_VERIFY
vco_clk_freq == 36'b0000000000000000000000000000000001010011011100100100111000000000
