bandwidth_mode == iopllwrap_bf::BANDWIDTH_MODE_AUTO
base_address == 16'd0
cascade_mode == iopllwrap_bf::CASCADE_MODE_STANDALONE
clk_switch_auto_en == iopllwrap_bf::CLK_SWITCH_AUTO_EN_FALSE
clk_switch_manual_en == iopllwrap_bf::CLK_SWITCH_MANUAL_EN_FALSE
compensation_clk_source == iopllwrap_bf::COMPENSATION_CLK_SOURCE_UNUSED
compensation_mode == iopllwrap_bf::COMPENSATION_MODE_DIRECT
f_max_pfd == 36'd325000000
f_max_vco == 36'd3200000000
f_min_pfd == 36'd10000000
f_min_vco == 36'd600000000
family == iopllwrap_bf::FAMILY_SM
fb_clk_delay == 32'd0
fb_clk_fractional_div_den == 32'd1
fb_clk_fractional_div_num == 32'd1
fb_clk_fractional_div_value == 32'd1
fb_clk_m_div == 9'd63
internal_base_address == 16'd2047
out_clk_0_c_div == 9'd9
out_clk_0_core_en == iopllwrap_bf::OUT_CLK_0_CORE_EN_TRUE
out_clk_0_delay == 32'd0
out_clk_0_dutycycle_den == 32'd18
out_clk_0_dutycycle_num == 32'd9
out_clk_0_dutycycle_percent == 32'd50
out_clk_0_freq == 36'd350000000
out_clk_0_phase_ps == 32'd0
out_clk_0_phase_shifts == 32'd0
out_clk_1_c_div == 9'd45
out_clk_1_core_en == iopllwrap_bf::OUT_CLK_1_CORE_EN_TRUE
out_clk_1_delay == 32'd0
out_clk_1_dutycycle_den == 32'd90
out_clk_1_dutycycle_num == 32'd45
out_clk_1_dutycycle_percent == 32'd50
out_clk_1_freq == 36'd70000000
out_clk_1_phase_ps == 32'd0
out_clk_1_phase_shifts == 32'd0
out_clk_2_c_div == 9'd1
out_clk_2_core_en == iopllwrap_bf::OUT_CLK_2_CORE_EN_FALSE
out_clk_2_delay == 32'd0
out_clk_2_dutycycle_den == 32'd4
out_clk_2_dutycycle_num == 32'd2
out_clk_2_dutycycle_percent == 32'd50
out_clk_2_freq == 36'd3150000000
out_clk_2_phase_ps == 32'd0
out_clk_2_phase_shifts == 32'd0
out_clk_3_c_div == 9'd1
out_clk_3_core_en == iopllwrap_bf::OUT_CLK_3_CORE_EN_FALSE
out_clk_3_delay == 32'd0
out_clk_3_dutycycle_den == 32'd4
out_clk_3_dutycycle_num == 32'd2
out_clk_3_dutycycle_percent == 32'd50
out_clk_3_freq == 36'd3150000000
out_clk_3_phase_ps == 32'd0
out_clk_3_phase_shifts == 32'd0
out_clk_4_c_div == 9'd1
out_clk_4_core_en == iopllwrap_bf::OUT_CLK_4_CORE_EN_FALSE
out_clk_4_delay == 32'd0
out_clk_4_dutycycle_den == 32'd4
out_clk_4_dutycycle_num == 32'd2
out_clk_4_dutycycle_percent == 32'd50
out_clk_4_freq == 36'd3150000000
out_clk_4_phase_ps == 32'd0
out_clk_4_phase_shifts == 32'd0
out_clk_5_c_div == 9'd1
out_clk_5_core_en == iopllwrap_bf::OUT_CLK_5_CORE_EN_FALSE
out_clk_5_delay == 32'd0
out_clk_5_dutycycle_den == 32'd4
out_clk_5_dutycycle_num == 32'd2
out_clk_5_dutycycle_percent == 32'd50
out_clk_5_freq == 36'd3150000000
out_clk_5_phase_ps == 32'd0
out_clk_5_phase_shifts == 32'd0
out_clk_6_c_div == 9'd1
out_clk_6_core_en == iopllwrap_bf::OUT_CLK_6_CORE_EN_FALSE
out_clk_6_delay == 32'd0
out_clk_6_dutycycle_den == 32'd4
out_clk_6_dutycycle_num == 32'd2
out_clk_6_dutycycle_percent == 32'd50
out_clk_6_freq == 36'd3150000000
out_clk_6_phase_ps == 32'd0
out_clk_6_phase_shifts == 32'd0
out_clk_cascading_source == iopllwrap_bf::OUT_CLK_CASCADING_SOURCE_UNUSED
out_clk_external_0_source == iopllwrap_bf::OUT_CLK_EXTERNAL_0_SOURCE_UNUSED
out_clk_external_1_source == iopllwrap_bf::OUT_CLK_EXTERNAL_1_SOURCE_UNUSED
out_clk_periph_0_delay == 32'd0
out_clk_periph_0_en == iopllwrap_bf::OUT_CLK_PERIPH_0_EN_TRUE
out_clk_periph_1_delay == 32'd0
out_clk_periph_1_en == iopllwrap_bf::OUT_CLK_PERIPH_1_EN_TRUE
pfd_clk_freq == 32'd50000000
powerdown_mode == iopllwrap_bf::FALSE
protocol_mode == iopllwrap_bf::PROTOCOL_MODE_BASIC
ref_clk_0_freq == 32'd100000000
ref_clk_1_freq == 32'd0
ref_clk_delay == 32'd0
ref_clk_n_div == 9'd2
self_reset_en == iopllwrap_bf::SELF_RESET_EN_FALSE
set_dutycycle == iopllwrap_bf::SET_DUTYCYCLE_FRACTION
set_fractional == iopllwrap_bf::SET_FRACTIONAL_FRACTION
set_freq == iopllwrap_bf::SET_FREQ_DIVISION_VERIFY
set_phase == iopllwrap_bf::SET_PHASE_NUM_SHIFTS_VERIFY
speed_grade == iopllwrap_bf::SPEED_GRADE_SPEEDGRADE2
vco_clk_freq == 36'd3150000000
xfpll_ctrl.avm_rd_pipestage == 2'd1
xfpll_ctrl.avm_wr_pipestage == 2'd1
xfpll_ctrl.avmm_base_addr == 11'd0
xfpll_ctrl.cp_specal_req == iopllwrap_fpll_ctrl::CP_SPECAL_REQ_ENABLE
xfpll_ctrl.dca_ddr_override == 6'd0
xfpll_ctrl.dca_loaden_override == 6'd0
xfpll_ctrl.dca_lvds_override == 6'd0
xfpll_ctrl.dcactrl_override == iopllwrap_fpll_ctrl::DCA_NO_OVERRIDE
xfpll_ctrl.dcc_delay == iopllwrap_fpll_ctrl::DCC_DELAY_ENABLE
xfpll_ctrl.dcc_dft_code_sel == iopllwrap_fpll_ctrl::DFT_CODE_OUT0
xfpll_ctrl.dcc_dfx_test_override == iopllwrap_fpll_ctrl::FSM_DFX_DISABLE
xfpll_ctrl.dcc_fsm_clk_divider == iopllwrap_fpll_ctrl::FSM_DCC_CLK_DIV4
xfpll_ctrl.dcc_load_en == iopllwrap_fpll_ctrl::DCC_LOAD_OFFSET_DISABLE
xfpll_ctrl.dcc_lock_criteria_sel == iopllwrap_fpll_ctrl::DCC_TIMEOUT
xfpll_ctrl.dcc_meas_ovrride == iopllwrap_fpll_ctrl::DCS_MEAS_OVR_DISABLE
xfpll_ctrl.dcc_meas_rod_code_override == 11'd0
xfpll_ctrl.dcc_result_accum_threshold == 4'd7
xfpll_ctrl.dcc_seq_dft_clk_sel == iopllwrap_fpll_ctrl::DISABLE_JITTER
xfpll_ctrl.dcc_slave_dly_safe_load == iopllwrap_fpll_ctrl::DCC_SAFE_LOAD_DISABLE
xfpll_ctrl.dcc_timeout_timer == 10'd400
xfpll_ctrl.dcc_wait_timer == 4'd8
xfpll_ctrl.dccdly_initcode == 4'd7
xfpll_ctrl.dcs_clk_sel == iopllwrap_fpll_ctrl::DCS_CLK_PLLVCOCLK
xfpll_ctrl.defer_calibration_usermode == iopllwrap_fpll_ctrl::DEFER_CAL_DISABLE
xfpll_ctrl.int_base_addr == 11'd2047
xfpll_ctrl.nreset_prgmnvrt == iopllwrap_fpll_ctrl::NRESET_NONINV
xfpll_ctrl.permitcal_override == iopllwrap_fpll_ctrl::PERMIT_CAL_DISABLE
xfpll_ctrl.pll_ctrl_override_setting == iopllwrap_fpll_ctrl::PLL_CTRL_ENABLE
xfpll_ctrl.pll_enable == iopllwrap_fpll_ctrl::PLL_ENABLED
xfpll_ctrl.pll_freqcal_req_flag == iopllwrap_fpll_ctrl::FREQCAL_REQ_FLAG_ENABLE
xfpll_ctrl.pll_lock_early_limit == iopllwrap_fpll_ctrl::LOCK_CNT_EARLY_LIMIT_256
xfpll_ctrl.pll_lock_final_adder_limit == iopllwrap_fpll_ctrl::LOCK_CNT_FINAL_ADDER_LIMIT_64
xfpll_ctrl.pll_lock_final_override == iopllwrap_fpll_ctrl::DCC_LOCK_IN
xfpll_ctrl.pll_lock_final_value == iopllwrap_fpll_ctrl::LOCK_FINAL_DISABLE
xfpll_ctrl.pll_slf_rst == iopllwrap_fpll_ctrl::PLL_SLF_RST_OFF
xfpll_ctrl.pll_test_enable == iopllwrap_fpll_ctrl::PLL_TESTEN_OFF
xfpll_ctrl.plniotri_override == iopllwrap_fpll_ctrl::PLNIOTRI_CTRL_DISABLE
xfpll_ctrl.powerdown_mode == iopllwrap_fpll_ctrl::FALSE
xfpll_ctrl.refclk_equal == iopllwrap_fpll_ctrl::REFCLK_EQUAL
xfpll_ctrl.specal_calibration_done == iopllwrap_fpll_ctrl::SPE_CALIBRATION_NOT_DONE
xfpll_ctrl.specal_calibration_error == iopllwrap_fpll_ctrl::SPE_CALIBRATION_GOOD
xfpll_ctrl.user_handle_calibration_fail == iopllwrap_fpll_ctrl::AUTO_RECAL
xfpll_ctrl.vccr_pd == iopllwrap_fpll_ctrl::VCCD_POWERUP
xiopll_custom.cal_converge == ioplltop_custom::CAL_NOT_CONVERGED
xiopll_custom.cal_done == ioplltop_custom::CAL_NOT_DONE
xiopll_custom.cal_error == ioplltop_custom::CAL_CLEAN
xiopll_custom.pll_freqcal_en == ioplltop_custom::FREQCAL_DISABLE
xiopll_custom.pll_freqcal_req_flag == ioplltop_custom::FREQCAL_REQ_FLAG_ENABLE
xiopll_custom.pll_reset_override_mode == ioplltop_custom::PLLRESETB
xiopll_custom.pll_vco_freq_band_0 == ioplltop_custom::PLL_FREQ_CLK0_BAND7
xiopll_custom.pll_vco_freq_band_1 == ioplltop_custom::PLL_FREQ_CLK1_BAND7
xiopll_custom.powerdown_mode == ioplltop_custom::FALSE
xiopll_custom.vco_bypass_en == ioplltop_custom::VCO_BYPASS_ENABLED
xiopll_custom.x221.phyfb_mux == ioplltop_fblvdsoutbuf_wrp::TIE_LO
xiopll_custom.x221.powerdown_mode == ioplltop_fblvdsoutbuf_wrp::FALSE
xiopll_custom.xccnt_iopll0.c_m_cnt_in_src == ioplltop_mcnt_wrp::C_M_CNT_IN_SRC_PH_MUX_CLK
xiopll_custom.xccnt_iopll0.c_m_cnt_ph_mux_prst == 3'd0
xiopll_custom.xccnt_iopll0.c_m_cnt_prst == 8'd1
xiopll_custom.xccnt_iopll0.cascade_ctrl == ioplltop_mcnt_wrp::CASCADE_DISABLED
xiopll_custom.xccnt_iopll0.ccnt_clkg == ioplltop_mcnt_wrp::CLK_GATING_DISABLED
xiopll_custom.xccnt_iopll0.coarse_dly == 32'd0
xiopll_custom.xccnt_iopll0.counter_dly == 32'd0
xiopll_custom.xccnt_iopll0.dprio_c_m_cnt_bypass_en == ioplltop_mcnt_wrp::DPRIO_CNT_DIV_ENABLED
xiopll_custom.xccnt_iopll0.dprio_c_m_cnt_even_duty_en == ioplltop_mcnt_wrp::DPRIO_CNT_EVEN_DUTY_ENABLED
xiopll_custom.xccnt_iopll0.dprio_c_m_cnt_hi_div_user == 8'd5
xiopll_custom.xccnt_iopll0.dprio_c_m_cnt_lo_div_user == 8'd4
xiopll_custom.xccnt_iopll0.dutycycle_den == 32'd18
xiopll_custom.xccnt_iopll0.dutycycle_num == 32'd9
xiopll_custom.xccnt_iopll0.fine_dly == 32'd0
xiopll_custom.xccnt_iopll0.phase_ps == 32'd0
xiopll_custom.xccnt_iopll0.phase_shifts == 32'd0
xiopll_custom.xccnt_iopll0.pll_coarse_dly == ioplltop_mcnt_wrp::PLL_COARSE_DLY_SETTING0
xiopll_custom.xccnt_iopll0.pll_fine_dly == ioplltop_mcnt_wrp::PLL_FINE_DLY_SETTING0
xiopll_custom.xccnt_iopll0.powerdown_mode == ioplltop_mcnt_wrp::FALSE
xiopll_custom.xccnt_iopll0.set_phase == ioplltop_mcnt_wrp::SET_PHASE_NUM_SHIFTS_VERIFY
xiopll_custom.xccnt_iopll0.vco_clk_freq == 36'd3150000000
xiopll_custom.xccnt_iopll1.c_m_cnt_in_src == ioplltop_mcnt_wrp::C_M_CNT_IN_SRC_PH_MUX_CLK
xiopll_custom.xccnt_iopll1.c_m_cnt_ph_mux_prst == 3'd0
xiopll_custom.xccnt_iopll1.c_m_cnt_prst == 8'd1
xiopll_custom.xccnt_iopll1.cascade_ctrl == ioplltop_mcnt_wrp::CASCADE_DISABLED
xiopll_custom.xccnt_iopll1.ccnt_clkg == ioplltop_mcnt_wrp::CLK_GATING_DISABLED
xiopll_custom.xccnt_iopll1.coarse_dly == 32'd0
xiopll_custom.xccnt_iopll1.counter_dly == 32'd0
xiopll_custom.xccnt_iopll1.dprio_c_m_cnt_bypass_en == ioplltop_mcnt_wrp::DPRIO_CNT_DIV_ENABLED
xiopll_custom.xccnt_iopll1.dprio_c_m_cnt_even_duty_en == ioplltop_mcnt_wrp::DPRIO_CNT_EVEN_DUTY_ENABLED
xiopll_custom.xccnt_iopll1.dprio_c_m_cnt_hi_div_user == 8'd23
xiopll_custom.xccnt_iopll1.dprio_c_m_cnt_lo_div_user == 8'd22
xiopll_custom.xccnt_iopll1.dutycycle_den == 32'd90
xiopll_custom.xccnt_iopll1.dutycycle_num == 32'd45
xiopll_custom.xccnt_iopll1.fine_dly == 32'd0
xiopll_custom.xccnt_iopll1.phase_ps == 32'd0
xiopll_custom.xccnt_iopll1.phase_shifts == 32'd0
xiopll_custom.xccnt_iopll1.pll_coarse_dly == ioplltop_mcnt_wrp::PLL_COARSE_DLY_SETTING0
xiopll_custom.xccnt_iopll1.pll_fine_dly == ioplltop_mcnt_wrp::PLL_FINE_DLY_SETTING0
xiopll_custom.xccnt_iopll1.powerdown_mode == ioplltop_mcnt_wrp::FALSE
xiopll_custom.xccnt_iopll1.set_phase == ioplltop_mcnt_wrp::SET_PHASE_NUM_SHIFTS_VERIFY
xiopll_custom.xccnt_iopll1.vco_clk_freq == 36'd3150000000
xiopll_custom.xccnt_iopll2.c_m_cnt_in_src == ioplltop_mcnt_wrp::C_M_CNT_IN_SRC_TEST_CLK
xiopll_custom.xccnt_iopll2.c_m_cnt_ph_mux_prst == 3'd0
xiopll_custom.xccnt_iopll2.c_m_cnt_prst == 8'd1
xiopll_custom.xccnt_iopll2.cascade_ctrl == ioplltop_mcnt_wrp::CASCADE_DISABLED
xiopll_custom.xccnt_iopll2.ccnt_clkg == ioplltop_mcnt_wrp::CLK_GATING_DISABLED
xiopll_custom.xccnt_iopll2.coarse_dly == 32'd0
xiopll_custom.xccnt_iopll2.counter_dly == 32'd0
xiopll_custom.xccnt_iopll2.dprio_c_m_cnt_bypass_en == ioplltop_mcnt_wrp::DPRIO_CNT_BYP_ENABLED
xiopll_custom.xccnt_iopll2.dprio_c_m_cnt_even_duty_en == ioplltop_mcnt_wrp::DPRIO_CNT_EVEN_DUTY_DISABLED
xiopll_custom.xccnt_iopll2.dprio_c_m_cnt_hi_div_user == 8'd1
xiopll_custom.xccnt_iopll2.dprio_c_m_cnt_lo_div_user == 8'd1
xiopll_custom.xccnt_iopll2.dutycycle_den == 32'd4
xiopll_custom.xccnt_iopll2.dutycycle_num == 32'd2
xiopll_custom.xccnt_iopll2.fine_dly == 32'd0
xiopll_custom.xccnt_iopll2.phase_ps == 32'd0
xiopll_custom.xccnt_iopll2.phase_shifts == 32'd0
xiopll_custom.xccnt_iopll2.pll_coarse_dly == ioplltop_mcnt_wrp::PLL_COARSE_DLY_SETTING0
xiopll_custom.xccnt_iopll2.pll_fine_dly == ioplltop_mcnt_wrp::PLL_FINE_DLY_SETTING0
xiopll_custom.xccnt_iopll2.powerdown_mode == ioplltop_mcnt_wrp::FALSE
xiopll_custom.xccnt_iopll2.set_phase == ioplltop_mcnt_wrp::SET_PHASE_NUM_SHIFTS_VERIFY
xiopll_custom.xccnt_iopll2.vco_clk_freq == 36'd3150000000
xiopll_custom.xccnt_iopll3.c_m_cnt_in_src == ioplltop_mcnt_wrp::C_M_CNT_IN_SRC_TEST_CLK
xiopll_custom.xccnt_iopll3.c_m_cnt_ph_mux_prst == 3'd0
xiopll_custom.xccnt_iopll3.c_m_cnt_prst == 8'd1
xiopll_custom.xccnt_iopll3.cascade_ctrl == ioplltop_mcnt_wrp::CASCADE_DISABLED
xiopll_custom.xccnt_iopll3.ccnt_clkg == ioplltop_mcnt_wrp::CLK_GATING_DISABLED
xiopll_custom.xccnt_iopll3.coarse_dly == 32'd0
xiopll_custom.xccnt_iopll3.counter_dly == 32'd0
xiopll_custom.xccnt_iopll3.dprio_c_m_cnt_bypass_en == ioplltop_mcnt_wrp::DPRIO_CNT_BYP_ENABLED
xiopll_custom.xccnt_iopll3.dprio_c_m_cnt_even_duty_en == ioplltop_mcnt_wrp::DPRIO_CNT_EVEN_DUTY_DISABLED
xiopll_custom.xccnt_iopll3.dprio_c_m_cnt_hi_div_user == 8'd1
xiopll_custom.xccnt_iopll3.dprio_c_m_cnt_lo_div_user == 8'd1
xiopll_custom.xccnt_iopll3.dutycycle_den == 32'd4
xiopll_custom.xccnt_iopll3.dutycycle_num == 32'd2
xiopll_custom.xccnt_iopll3.fine_dly == 32'd0
xiopll_custom.xccnt_iopll3.phase_ps == 32'd0
xiopll_custom.xccnt_iopll3.phase_shifts == 32'd0
xiopll_custom.xccnt_iopll3.pll_coarse_dly == ioplltop_mcnt_wrp::PLL_COARSE_DLY_SETTING0
xiopll_custom.xccnt_iopll3.pll_fine_dly == ioplltop_mcnt_wrp::PLL_FINE_DLY_SETTING0
xiopll_custom.xccnt_iopll3.powerdown_mode == ioplltop_mcnt_wrp::FALSE
xiopll_custom.xccnt_iopll3.set_phase == ioplltop_mcnt_wrp::SET_PHASE_NUM_SHIFTS_VERIFY
xiopll_custom.xccnt_iopll3.vco_clk_freq == 36'd3150000000
xiopll_custom.xccnt_iopll4.c_m_cnt_in_src == ioplltop_mcnt_wrp::C_M_CNT_IN_SRC_TEST_CLK
xiopll_custom.xccnt_iopll4.c_m_cnt_ph_mux_prst == 3'd0
xiopll_custom.xccnt_iopll4.c_m_cnt_prst == 8'd1
xiopll_custom.xccnt_iopll4.cascade_ctrl == ioplltop_mcnt_wrp::CASCADE_DISABLED
xiopll_custom.xccnt_iopll4.ccnt_clkg == ioplltop_mcnt_wrp::CLK_GATING_DISABLED
xiopll_custom.xccnt_iopll4.coarse_dly == 32'd0
xiopll_custom.xccnt_iopll4.counter_dly == 32'd0
xiopll_custom.xccnt_iopll4.dprio_c_m_cnt_bypass_en == ioplltop_mcnt_wrp::DPRIO_CNT_BYP_ENABLED
xiopll_custom.xccnt_iopll4.dprio_c_m_cnt_even_duty_en == ioplltop_mcnt_wrp::DPRIO_CNT_EVEN_DUTY_DISABLED
xiopll_custom.xccnt_iopll4.dprio_c_m_cnt_hi_div_user == 8'd1
xiopll_custom.xccnt_iopll4.dprio_c_m_cnt_lo_div_user == 8'd1
xiopll_custom.xccnt_iopll4.dutycycle_den == 32'd4
xiopll_custom.xccnt_iopll4.dutycycle_num == 32'd2
xiopll_custom.xccnt_iopll4.fine_dly == 32'd0
xiopll_custom.xccnt_iopll4.phase_ps == 32'd0
xiopll_custom.xccnt_iopll4.phase_shifts == 32'd0
xiopll_custom.xccnt_iopll4.pll_coarse_dly == ioplltop_mcnt_wrp::PLL_COARSE_DLY_SETTING0
xiopll_custom.xccnt_iopll4.pll_fine_dly == ioplltop_mcnt_wrp::PLL_FINE_DLY_SETTING0
xiopll_custom.xccnt_iopll4.powerdown_mode == ioplltop_mcnt_wrp::FALSE
xiopll_custom.xccnt_iopll4.set_phase == ioplltop_mcnt_wrp::SET_PHASE_NUM_SHIFTS_VERIFY
xiopll_custom.xccnt_iopll4.vco_clk_freq == 36'd3150000000
xiopll_custom.xccnt_iopll5.c_m_cnt_in_src == ioplltop_mcnt_wrp::C_M_CNT_IN_SRC_TEST_CLK
xiopll_custom.xccnt_iopll5.c_m_cnt_ph_mux_prst == 3'd0
xiopll_custom.xccnt_iopll5.c_m_cnt_prst == 8'd1
xiopll_custom.xccnt_iopll5.cascade_ctrl == ioplltop_mcnt_wrp::CASCADE_DISABLED
xiopll_custom.xccnt_iopll5.ccnt_clkg == ioplltop_mcnt_wrp::CLK_GATING_DISABLED
xiopll_custom.xccnt_iopll5.coarse_dly == 32'd0
xiopll_custom.xccnt_iopll5.counter_dly == 32'd0
xiopll_custom.xccnt_iopll5.dprio_c_m_cnt_bypass_en == ioplltop_mcnt_wrp::DPRIO_CNT_BYP_ENABLED
xiopll_custom.xccnt_iopll5.dprio_c_m_cnt_even_duty_en == ioplltop_mcnt_wrp::DPRIO_CNT_EVEN_DUTY_DISABLED
xiopll_custom.xccnt_iopll5.dprio_c_m_cnt_hi_div_user == 8'd1
xiopll_custom.xccnt_iopll5.dprio_c_m_cnt_lo_div_user == 8'd1
xiopll_custom.xccnt_iopll5.dutycycle_den == 32'd4
xiopll_custom.xccnt_iopll5.dutycycle_num == 32'd2
xiopll_custom.xccnt_iopll5.fine_dly == 32'd0
xiopll_custom.xccnt_iopll5.phase_ps == 32'd0
xiopll_custom.xccnt_iopll5.phase_shifts == 32'd0
xiopll_custom.xccnt_iopll5.pll_coarse_dly == ioplltop_mcnt_wrp::PLL_COARSE_DLY_SETTING0
xiopll_custom.xccnt_iopll5.pll_fine_dly == ioplltop_mcnt_wrp::PLL_FINE_DLY_SETTING0
xiopll_custom.xccnt_iopll5.powerdown_mode == ioplltop_mcnt_wrp::FALSE
xiopll_custom.xccnt_iopll5.set_phase == ioplltop_mcnt_wrp::SET_PHASE_NUM_SHIFTS_VERIFY
xiopll_custom.xccnt_iopll5.vco_clk_freq == 36'd3150000000
xiopll_custom.xccnt_iopll6.c_m_cnt_in_src == ioplltop_mcnt_wrp::C_M_CNT_IN_SRC_TEST_CLK
xiopll_custom.xccnt_iopll6.c_m_cnt_ph_mux_prst == 3'd0
xiopll_custom.xccnt_iopll6.c_m_cnt_prst == 8'd1
xiopll_custom.xccnt_iopll6.cascade_ctrl == ioplltop_mcnt_wrp::CASCADE_DISABLED
xiopll_custom.xccnt_iopll6.ccnt_clkg == ioplltop_mcnt_wrp::CLK_GATING_DISABLED
xiopll_custom.xccnt_iopll6.coarse_dly == 32'd0
xiopll_custom.xccnt_iopll6.counter_dly == 32'd0
xiopll_custom.xccnt_iopll6.dprio_c_m_cnt_bypass_en == ioplltop_mcnt_wrp::DPRIO_CNT_BYP_ENABLED
xiopll_custom.xccnt_iopll6.dprio_c_m_cnt_even_duty_en == ioplltop_mcnt_wrp::DPRIO_CNT_EVEN_DUTY_DISABLED
xiopll_custom.xccnt_iopll6.dprio_c_m_cnt_hi_div_user == 8'd1
xiopll_custom.xccnt_iopll6.dprio_c_m_cnt_lo_div_user == 8'd1
xiopll_custom.xccnt_iopll6.dutycycle_den == 32'd4
xiopll_custom.xccnt_iopll6.dutycycle_num == 32'd2
xiopll_custom.xccnt_iopll6.fine_dly == 32'd0
xiopll_custom.xccnt_iopll6.phase_ps == 32'd0
xiopll_custom.xccnt_iopll6.phase_shifts == 32'd0
xiopll_custom.xccnt_iopll6.pll_coarse_dly == ioplltop_mcnt_wrp::PLL_COARSE_DLY_SETTING0
xiopll_custom.xccnt_iopll6.pll_fine_dly == ioplltop_mcnt_wrp::PLL_FINE_DLY_SETTING0
xiopll_custom.xccnt_iopll6.powerdown_mode == ioplltop_mcnt_wrp::FALSE
xiopll_custom.xccnt_iopll6.set_phase == ioplltop_mcnt_wrp::SET_PHASE_NUM_SHIFTS_VERIFY
xiopll_custom.xccnt_iopll6.vco_clk_freq == 36'd3150000000
xiopll_custom.xcoutbuf0.extclk_dllout_en == ioplltop_coutbuf_wrp::EXTCLK_DLLOUT_DISABLE
xiopll_custom.xcoutbuf0.powerdown_mode == ioplltop_coutbuf_wrp::FALSE
xiopll_custom.xcoutbuf1.extclk_dllout_en == ioplltop_coutbuf_wrp::EXTCLK_DLLOUT_DISABLE
xiopll_custom.xcoutbuf1.powerdown_mode == ioplltop_coutbuf_wrp::FALSE
xiopll_custom.xcoutbuf2.extclk_dllout_en == ioplltop_coutbuf_wrp::EXTCLK_DLLOUT_DISABLE
xiopll_custom.xcoutbuf2.powerdown_mode == ioplltop_coutbuf_wrp::FALSE
xiopll_custom.xcoutbuf3.extclk_dllout_en == ioplltop_coutbuf_wrp::EXTCLK_DLLOUT_DISABLE
xiopll_custom.xcoutbuf3.powerdown_mode == ioplltop_coutbuf_wrp::FALSE
xiopll_custom.xdca0.dca_cb_tuning == 2'd0
xiopll_custom.xdca0.dca_clk_bypass == ioplltop_dcaana_wrp::DCA_CLK_BYPASS_DIS
xiopll_custom.xdca0.dca_pulldn_en == ioplltop_dcaana_wrp::DCA_PULLDOWN_ENABLED
xiopll_custom.xdca0.dca_pullup_en == ioplltop_dcaana_wrp::DCA_PULLUP_ENABLED
xiopll_custom.xdca0.powerdown_mode == ioplltop_dcaana_wrp::FALSE
xiopll_custom.xdca1.dca_cb_tuning == 2'd0
xiopll_custom.xdca1.dca_clk_bypass == ioplltop_dcaana_wrp::DCA_CLK_BYPASS_DIS
xiopll_custom.xdca1.dca_pulldn_en == ioplltop_dcaana_wrp::DCA_PULLDOWN_ENABLED
xiopll_custom.xdca1.dca_pullup_en == ioplltop_dcaana_wrp::DCA_PULLUP_ENABLED
xiopll_custom.xdca1.powerdown_mode == ioplltop_dcaana_wrp::FALSE
xiopll_custom.xdcavco.dca_cb_tuning == 2'd0
xiopll_custom.xdcavco.dca_clk_bypass == ioplltop_dcaana_wrp::DCA_CLK_BYPASS_DIS
xiopll_custom.xdcavco.dca_pulldn_en == ioplltop_dcaana_wrp::DCA_PULLDOWN_ENABLED
xiopll_custom.xdcavco.dca_pullup_en == ioplltop_dcaana_wrp::DCA_PULLUP_ENABLED
xiopll_custom.xdcavco.powerdown_mode == ioplltop_dcaana_wrp::FALSE
xiopll_custom.xdcs_top.dcs_delay_en == ioplltop_pll_dcstop_wrp::DCA_DELAY_ENABLED
xiopll_custom.xdcs_top.dcs_dft_clk_sel == ioplltop_pll_dcstop_wrp::DCS_DFT_CLK_SEL0
xiopll_custom.xdcs_top.dcs_dly_driven == ioplltop_pll_dcstop_wrp::DCS_DELAY_DRIVEN0
xiopll_custom.xdcs_top.dcs_dly_setting == ioplltop_pll_dcstop_wrp::DCS_DELAY_SETTING0
xiopll_custom.xdcs_top.dcs_obs_en == ioplltop_pll_dcstop_wrp::DCS_OBS_DISABLED
xiopll_custom.xdcs_top.jittermode_insel == ioplltop_pll_dcstop_wrp::DCS_JITTER_MODE_CLOCK_UNDER_TEST
xiopll_custom.xdcs_top.powerdown_mode == ioplltop_pll_dcstop_wrp::FALSE
xiopll_custom.xextclk0.pll_extclk_0_0_cnt_src == ioplltop_extclk_wrp::PLL_EXTCLK_CNT_SRC_DFT_IN_0
xiopll_custom.xextclk0.pll_extclk_enable == ioplltop_extclk_wrp::PLL_EXTCLKEN_DISABLE
xiopll_custom.xextclk0.pll_extclk_prgmnvrt == ioplltop_extclk_wrp::PLL_EXTCLK_NON_INV
xiopll_custom.xextclk0.powerdown_mode == ioplltop_extclk_wrp::FALSE
xiopll_custom.xextclk1.pll_extclk_0_0_cnt_src == ioplltop_extclk_wrp::PLL_EXTCLK_CNT_SRC_DFT_IN_0
xiopll_custom.xextclk1.pll_extclk_enable == ioplltop_extclk_wrp::PLL_EXTCLKEN_DISABLE
xiopll_custom.xextclk1.pll_extclk_prgmnvrt == ioplltop_extclk_wrp::PLL_EXTCLK_NON_INV
xiopll_custom.xextclk1.powerdown_mode == ioplltop_extclk_wrp::FALSE
xiopll_custom.xfine_dly_0.coarse_dly == 32'd0
xiopll_custom.xfine_dly_0.counter_dly == 32'd0
xiopll_custom.xfine_dly_0.fine_dly == 32'd0
xiopll_custom.xfine_dly_0.pll_coarse_dly == ioplltop_fine_dly_wrap::PLL_COARSE_DLY_SETTING0
xiopll_custom.xfine_dly_0.pll_dly_enable_disable == ioplltop_fine_dly_wrap::PLL_DLY_ENABLE
xiopll_custom.xfine_dly_0.pll_fine_dly == ioplltop_fine_dly_wrap::PLL_FINE_DLY_SETTING0
xiopll_custom.xfine_dly_0.powerdown_mode == ioplltop_fine_dly_wrap::FALSE
xiopll_custom.xfine_dly_1.coarse_dly == 32'd0
xiopll_custom.xfine_dly_1.counter_dly == 32'd0
xiopll_custom.xfine_dly_1.fine_dly == 32'd0
xiopll_custom.xfine_dly_1.pll_coarse_dly == ioplltop_fine_dly_wrap::PLL_COARSE_DLY_SETTING0
xiopll_custom.xfine_dly_1.pll_dly_enable_disable == ioplltop_fine_dly_wrap::PLL_DLY_ENABLE
xiopll_custom.xfine_dly_1.pll_fine_dly == ioplltop_fine_dly_wrap::PLL_FINE_DLY_SETTING0
xiopll_custom.xfine_dly_1.powerdown_mode == ioplltop_fine_dly_wrap::FALSE
xiopll_custom.xiopll_core.powerdown_mode == ioplltop_core::FALSE
xiopll_custom.xiopll_core.gdiv.c_m_cnt_in_src == ioplltop_fbgen_wrp::C_M_CNT_IN_SRC_PH_MUX_CLK
xiopll_custom.xiopll_core.gdiv.dprio_c_m_cnt_bypass_en == ioplltop_fbgen_wrp::DPRIO_CNT_DIV_ENABLED
xiopll_custom.xiopll_core.gdiv.dprio_c_m_cnt_hi_div_user == 9'd63
xiopll_custom.xiopll_core.gdiv.powerdown_mode == ioplltop_fbgen_wrp::FALSE
xiopll_custom.xiopll_core.iadc.adc_chopen == ioplltop_adcsdmod10top_wrp::ADC_CHOP_DISABLED
xiopll_custom.xiopll_core.iadc.adc_clkdiv_bypass == ioplltop_adcsdmod10top_wrp::ADC_ENABLE_CLKDIV
xiopll_custom.xiopll_core.iadc.adc_clkdiv_ctrl == ioplltop_adcsdmod10top_wrp::ADC_DIVIDE_BY_4
xiopll_custom.xiopll_core.iadc.adc_en == ioplltop_adcsdmod10top_wrp::ADC_DISABLED
xiopll_custom.xiopll_core.iadc.adc_endizz == ioplltop_adcsdmod10top_wrp::ADC_DISABLED_NOISE_INJECTION
xiopll_custom.xiopll_core.iadc.adc_freeze_ctrl == ioplltop_adcsdmod10top_wrp::ADC_FREEZE_DISABLED
xiopll_custom.xiopll_core.iadc.adc_nbias_adjust == ioplltop_adcsdmod10top_wrp::ADC_NBIAS_ADJUSTMENT_DISABLED
xiopll_custom.xiopll_core.iadc.adc_pbias_adjust == ioplltop_adcsdmod10top_wrp::ADC_PBIAS_ADJUSTMENT_DISABLED
xiopll_custom.xiopll_core.iadc.adc_startcount == ioplltop_adcsdmod10top_wrp::ADC_STOP_COUNT
xiopll_custom.xiopll_core.iadc.powerdown_mode == ioplltop_adcsdmod10top_wrp::FALSE
xiopll_custom.xiopll_core.ipllljtopana.powerdown_mode == ioplltop_pllljtopana::FALSE
xiopll_custom.xiopll_core.ipllljtopana.vco.iref2_nlvcascode_cfg == ioplltop_vco_wrp::IREF2_DEGENERATIVE_SETTING0
xiopll_custom.xiopll_core.ipllljtopana.vco.ljpll_iref2_en == ioplltop_vco_wrp::VCO_IREF2_DISABLED
xiopll_custom.xiopll_core.ipllljtopana.vco.ljpll_iref2_nlvcascode_byp == ioplltop_vco_wrp::VCO_IREF2_DEGEN_DISABLED
xiopll_custom.xiopll_core.ipllljtopana.vco.ljpll_vco_rdac2vctl_en == ioplltop_vco_wrp::VCO_RDAC2VCTL_DISABLED
xiopll_custom.xiopll_core.ipllljtopana.vco.ljpll_vco_vctl_pullup == ioplltop_vco_wrp::VCO_VCTRL_PULLUP_DISABLED
xiopll_custom.xiopll_core.ipllljtopana.vco.ljpll_vco_vctlrdac == ioplltop_vco_wrp::VCO_VCTRLDAC_SETTING8
xiopll_custom.xiopll_core.ipllljtopana.vco.pll_vco_ph0_en == ioplltop_vco_wrp::PLL_VCO_PH0_EN
xiopll_custom.xiopll_core.ipllljtopana.vco.pll_vco_ph1_en == ioplltop_vco_wrp::PLL_VCO_PH1_EN
xiopll_custom.xiopll_core.ipllljtopana.vco.pll_vco_ph2_en == ioplltop_vco_wrp::PLL_VCO_PH2_EN
xiopll_custom.xiopll_core.ipllljtopana.vco.pll_vco_ph3_en == ioplltop_vco_wrp::PLL_VCO_PH3_EN
xiopll_custom.xiopll_core.ipllljtopana.vco.pll_vco_ph4_en == ioplltop_vco_wrp::PLL_VCO_PH4_EN
xiopll_custom.xiopll_core.ipllljtopana.vco.pll_vco_ph5_en == ioplltop_vco_wrp::PLL_VCO_PH5_EN
xiopll_custom.xiopll_core.ipllljtopana.vco.pll_vco_ph6_en == ioplltop_vco_wrp::PLL_VCO_PH6_EN
xiopll_custom.xiopll_core.ipllljtopana.vco.pll_vco_ph7_en == ioplltop_vco_wrp::PLL_VCO_PH7_EN
xiopll_custom.xiopll_core.ipllljtopana.vco.powerdown_mode == ioplltop_vco_wrp::FALSE
xiopll_custom.xiopll_core.ipllljtopana.vco.vco_clk_div1248 == ioplltop_vco_wrp::VCO_IREF1_DIV8_ENABLED
xiopll_custom.xiopll_core.ipllljtopana.vco.vco_vctrldac_en == ioplltop_vco_wrp::VCO_VCTRLDAC_DISABLED
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.iref1_trim_prdv == ioplltop_chgpmplf_wrp::PLL_IREF1_MIRROR_SETTING0
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.iref1_trim_rdac == ioplltop_chgpmplf_wrp::PLL_IREF1_BASE_SETTING0
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_cp_specal_stepnum == ioplltop_chgpmplf_wrp::SPE_CORRECTION_SETTING0
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_cpi_nbstk == ioplltop_chgpmplf_wrp::PLL_CPI_NBSTK_SETTING0
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_cpi_trim == ioplltop_chgpmplf_wrp::CPI_TRIM_SETTING6
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_cpintsf_en == ioplltop_chgpmplf_wrp::PLL_CP_INTSF_ENABLE
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_cpp_nbstk == ioplltop_chgpmplf_wrp::PLL_CPP_NBSTK_SETTING0
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_cpp_trim == ioplltop_chgpmplf_wrp::CPP_TRIM_SETTING9
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_cr_lockrst_ovvrd == ioplltop_chgpmplf_wrp::PLL_LOCK_RESET_OVD0
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_iref1_bypassamp_mode == ioplltop_chgpmplf_wrp::PLL_IREF1_AMP_ENABLE
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_iref1_en == ioplltop_chgpmplf_wrp::PLL_IREF1_ENABLE
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_iref1_rmode_en == ioplltop_chgpmplf_wrp::PLL_IREF1_RMODE_DISABLE
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_lock_fltr_test == ioplltop_chgpmplf_wrp::PLL_LOCK_FLTR_NRM
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_lockthresh == ioplltop_chgpmplf_wrp::PLL_PFD_LOCKTHRESH_SETTING14
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_lpf_pgcntl == ioplltop_chgpmplf_wrp::PLL_RST_PWRGATING_SETTING1
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_lpf_trim == ioplltop_chgpmplf_wrp::PLL_LPF_ITRIM_SETTING1
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_residual_pw == ioplltop_chgpmplf_wrp::PLL_PFD_RESIDUAL_PW_SETTING2
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_specal_en == ioplltop_chgpmplf_wrp::PLL_CP_SPECAL_DISABLE
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_specal_stepsize == ioplltop_chgpmplf_wrp::PLL_SPECAL_CB_SETTING0
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_spemeas_en == ioplltop_chgpmplf_wrp::PLL_CP_SPEMEAS_DISABLE
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_spemeas_tdccal_en == ioplltop_chgpmplf_wrp::PLL_SPEMEAS_TDCCAL_DISABLE
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_spemeas_tdctrim == ioplltop_chgpmplf_wrp::PLL_SPEMEAS_TDCTRIM_SETTING0
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_testdn_enable == ioplltop_chgpmplf_wrp::PLL_TESTDNEN_OFF
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.pll_testup_enable == ioplltop_chgpmplf_wrp::PLL_TESTUPEN_OFF
xiopll_custom.xiopll_core.ipllljtopana.xchgpmplf.powerdown_mode == ioplltop_chgpmplf_wrp::FALSE
xiopll_custom.xiopll_core.xatb_iopll.iopll_atb == ioplltop_atb_iopll_wrp::ATB_SELECTDISABLE
xiopll_custom.xiopll_core.xatb_iopll.powerdown_mode == ioplltop_atb_iopll_wrp::FALSE
xiopll_custom.xiopll_core.xfb.coarse_dly == 32'd0
xiopll_custom.xiopll_core.xfb.counter_dly == 32'd0
xiopll_custom.xiopll_core.xfb.fine_dly == 32'd0
xiopll_custom.xiopll_core.xfb.main_coarse_dly == 32'd0
xiopll_custom.xiopll_core.xfb.pll_cmp_buf_dly == ioplltop_fb_wrp::PLL_CMP_BUF_DLY_SETTING0
xiopll_custom.xiopll_core.xfb.pll_coarse_dly == ioplltop_fb_wrp::PLL_COARSE_DLY_SETTING0
xiopll_custom.xiopll_core.xfb.pll_fbclk_mux_1 == ioplltop_fb_wrp::PLL_FBCLK_MUX_1_GLB
xiopll_custom.xiopll_core.xfb.pll_fbclk_mux_2 == ioplltop_fb_wrp::PLL_FBCLK_MUX_2_M_CNT
xiopll_custom.xiopll_core.xfb.pll_fine_dly == ioplltop_fb_wrp::PLL_FINE_DLY_SETTING0
xiopll_custom.xiopll_core.xfb.powerdown_mode == ioplltop_fb_wrp::FALSE
xiopll_custom.xiopll_core.xfine_dly_n.coarse_dly == 32'd0
xiopll_custom.xiopll_core.xfine_dly_n.counter_dly == 32'd0
xiopll_custom.xiopll_core.xfine_dly_n.fine_dly == 32'd0
xiopll_custom.xiopll_core.xfine_dly_n.pll_coarse_dly == ioplltop_fine_dly_wrap1::PLL_COARSE_DLY_SETTING0
xiopll_custom.xiopll_core.xfine_dly_n.pll_fine_dly == ioplltop_fine_dly_wrap1::PLL_FINE_DLY_SETTING0
xiopll_custom.xiopll_core.xfine_dly_n.powerdown_mode == ioplltop_fine_dly_wrap1::FALSE
xiopll_custom.xiopll_core.xncnt_iopll.pll_n_cnt_bypass_en == ioplltop_ncnt_wrp::PLL_N_CNT_DIV_ENABLED
xiopll_custom.xiopll_core.xncnt_iopll.pll_n_cnt_hi_div == 8'd1
xiopll_custom.xiopll_core.xncnt_iopll.pll_n_cnt_lo_div == 8'd1
xiopll_custom.xiopll_core.xncnt_iopll.pll_n_cnt_odd_div_duty_en == ioplltop_ncnt_wrp::PLL_N_CNT_EVEN_DUTY_DISABLED
xiopll_custom.xiopll_core.xncnt_iopll.powerdown_mode == ioplltop_ncnt_wrp::FALSE
xiopll_custom.xiopll_core.xref.main_coarse_dly == 32'd0
xiopll_custom.xiopll_core.xref.pll_ref_buf_dly == ioplltop_ref_wrp::PLL_REF_BUF_DLY_SETTING0
xiopll_custom.xiopll_core.xref.powerdown_mode == ioplltop_ref_wrp::FALSE
xiopll_custom.xiopll_core.xtestmux.pll_tclk_mux_en == ioplltop_testmux_wrp::PLL_TCLK_MUX_DISABLED
xiopll_custom.xiopll_core.xtestmux.pll_tclk_sel == ioplltop_testmux_wrp::PLL_TCLK_N_SRC
xiopll_custom.xiopll_core.xtestmux.powerdown_mode == ioplltop_testmux_wrp::FALSE
xiopll_custom.xpllcoutbuf0.cnt_out_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_ENABLE
xiopll_custom.xpllcoutbuf0.cnt_out_global_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_GBL_ENABLE
xiopll_custom.xpllcoutbuf0.dft_ppmclk == ioplltop_pllcoutbuf_wrp::C_CNT_OUT
xiopll_custom.xpllcoutbuf0.powerdown_mode == ioplltop_pllcoutbuf_wrp::FALSE
xiopll_custom.xpllcoutbuf1.cnt_out_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_ENABLE
xiopll_custom.xpllcoutbuf1.cnt_out_global_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_GBL_ENABLE
xiopll_custom.xpllcoutbuf1.dft_ppmclk == ioplltop_pllcoutbuf_wrp::C_CNT_OUT
xiopll_custom.xpllcoutbuf1.powerdown_mode == ioplltop_pllcoutbuf_wrp::FALSE
xiopll_custom.xpllcoutbuf2.cnt_out_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_DISABLE
xiopll_custom.xpllcoutbuf2.cnt_out_global_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_GBL_ENABLE
xiopll_custom.xpllcoutbuf2.dft_ppmclk == ioplltop_pllcoutbuf_wrp::C_CNT_OUT
xiopll_custom.xpllcoutbuf2.powerdown_mode == ioplltop_pllcoutbuf_wrp::FALSE
xiopll_custom.xpllcoutbuf3.cnt_out_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_DISABLE
xiopll_custom.xpllcoutbuf3.cnt_out_global_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_GBL_ENABLE
xiopll_custom.xpllcoutbuf3.dft_ppmclk == ioplltop_pllcoutbuf_wrp::C_CNT_OUT
xiopll_custom.xpllcoutbuf3.powerdown_mode == ioplltop_pllcoutbuf_wrp::FALSE
xiopll_custom.xpllcoutbuf4.cnt_out_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_DISABLE
xiopll_custom.xpllcoutbuf4.cnt_out_global_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_GBL_ENABLE
xiopll_custom.xpllcoutbuf4.dft_ppmclk == ioplltop_pllcoutbuf_wrp::C_CNT_OUT
xiopll_custom.xpllcoutbuf4.powerdown_mode == ioplltop_pllcoutbuf_wrp::FALSE
xiopll_custom.xpllcoutbuf5.cnt_out_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_DISABLE
xiopll_custom.xpllcoutbuf5.cnt_out_global_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_GBL_ENABLE
xiopll_custom.xpllcoutbuf5.dft_ppmclk == ioplltop_pllcoutbuf_wrp::C_CNT_OUT
xiopll_custom.xpllcoutbuf5.powerdown_mode == ioplltop_pllcoutbuf_wrp::FALSE
xiopll_custom.xpllcoutbuf6.cnt_out_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_DISABLE
xiopll_custom.xpllcoutbuf6.cnt_out_global_en == ioplltop_pllcoutbuf_wrp::CNT_OUTPUT_GBL_ENABLE
xiopll_custom.xpllcoutbuf6.dft_ppmclk == ioplltop_pllcoutbuf_wrp::C_CNT_OUT
xiopll_custom.xpllcoutbuf6.powerdown_mode == ioplltop_pllcoutbuf_wrp::FALSE
xiopll_custom.xpm_pll_so.pll_auto_clk_sw_en == ioplltop_pll_so_wrp::PLL_AUTO_CLK_SW_DISABLED
xiopll_custom.xpm_pll_so.pll_clk_loss_edge == ioplltop_pll_so_wrp::PLL_CLK_LOSS_RISING_EDGE
xiopll_custom.xpm_pll_so.pll_clk_loss_sw_en == ioplltop_pll_so_wrp::PLL_CLK_LOSS_SW_BYPS
xiopll_custom.xpm_pll_so.pll_clk_sel_override == ioplltop_pll_so_wrp::PLL_CLK_SEL_OVERRIDE_DIS
xiopll_custom.xpm_pll_so.pll_clk_sel_override_value == ioplltop_pll_so_wrp::PLL_CLK_SEL_OVERRIDE_CLK0
xiopll_custom.xpm_pll_so.pll_clk_sw_dly == ioplltop_pll_so_wrp::PLL_CLK_SW_DELAYED0
xiopll_custom.xpm_pll_so.pll_clkloss_fltr_sel == ioplltop_pll_so_wrp::PLL_CLKLOSS_FLTR_SETTING0
xiopll_custom.xpm_pll_so.pll_extswitch_ovrd == ioplltop_pll_so_wrp::PLL_EXTSWITCH_OVERRIDE_DIS
xiopll_custom.xpm_pll_so.pll_manu_clk_sw_en == ioplltop_pll_so_wrp::PLL_MANU_CLK_SW_DISABLED
xiopll_custom.xpm_pll_so.pll_sw_refclk_src == ioplltop_pll_so_wrp::PLL_SW_REFCLK_SRC_CLK_0
xiopll_custom.xpm_pll_so.powerdown_mode == ioplltop_pll_so_wrp::FALSE
xiopll_custom.xvco_cal.freqcal_rstb == ioplltop_vco_cal_cnt_wrp::FREQCAL_RESET
xiopll_custom.xvco_cal.freqcnt_val == 4'd0
xiopll_custom.xvco_cal.freqmeas_en == ioplltop_vco_cal_cnt_wrp::FREQMEAS_DISABLED
xiopll_custom.xvco_cal.powerdown_mode == ioplltop_vco_cal_cnt_wrp::FALSE
xiopll_custom.xvreg_1p0.powerdown_mode == ioplltop_vreg_20ma_wrap_wrp::FALSE
xiopll_custom.xvreg_1p0.vccdreg_cal == ioplltop_vreg_20ma_wrap_wrp::VCCDREG_SETTING0
xiopll_custom.xvreg_1p0.vreg_adc_viewsel_cfg == ioplltop_vreg_20ma_wrap_wrp::VREG_ADC_VIEWSEL_SETTING0
xiopll_custom.xvreg_1p0.vreg_lkr_mode_en == ioplltop_vreg_20ma_wrap_wrp::LEAKER_ENABLED
xiopll_custom.xvreg_1p0.vreg_lkr_strength_cfg == ioplltop_vreg_20ma_wrap_wrp::LEAKER_CFG1
xiopll_custom.xvreg_1p0.vreg_override == ioplltop_vreg_20ma_wrap_wrp::OVR_DISABLED
xiopll_custom.xvreg_1p0.vreg_rcompensation_en == ioplltop_vreg_20ma_wrap_wrp::RCOMPENSATION_SETTING1
