a_cfg_auxm_cal_rsvd == 6'd0
a_cfg_auxm_obuf_rsvd == 3'd0
a_cfg_auxm_rsvd == 28'd0
a_cfg_auxmgr_addr == 6'd0
a_cfg_auxmgr_dbase_addr == 6'd54
a_cfg_auxmgr_ddec_en == uibph2ssmwrp::CFG_DIS
a_cfg_auxmgr_dlimit_addr == 6'd58
a_cfg_auxmgr_rd_dly == 5'd16
a_cfg_auxmgr_type == uibph2ssmwrp::UNASSIGNED
a_dummy_vcomp_rcomp_code_pd == uibph2ssmwrp::LO_PD
a_dummyvcomp_rcomp_code_pu0 == uibph2ssmwrp::LO_PU0
a_dummyvcomp_rcomp_code_pu1 == uibph2ssmwrp::LO_PU1
a_dummyvcomp_rcomp_code_pu2 == uibph2ssmwrp::LO_PU2
a_dummyvcomp_rcomp_code_pu3 == uibph2ssmwrp::LO_PU3
a_dummyvcomp_rcomp_code_pu4 == uibph2ssmwrp::LO_PU4
a_dummyvcomp_rcomp_code_pu5 == uibph2ssmwrp::LO_PU5
a_dummyvcomp_rcomp_code_pu6 == uibph2ssmwrp::LO_PU6
a_dummyvcomp_rcomp_code_pu7 == uibph2ssmwrp::LO_PU7
a_sup_mode == uibph2ssmwrp::PRODUCTION_MODE
a_uib_mode == uibph2ssmwrp::A_UIB_MODE_HBM2E
auxm_cfg_auxm_spare == 32'd0
auxm_dprio_aux_addr == 9'd0
auxm_dprio_aux_start == uibph2ssmwrp::AUX_DPRIO_START
auxm_dprio_aux_wait_rd == uibph2ssmwrp::AUX_DPRIO_NO_WAIT_RD
auxm_dprio_aux_wait_wr == uibph2ssmwrp::AUX_DPRIO_NO_WAIT_WR
auxm_dprio_aux_wr_data == 8'd0
auxm_dprio_aux_wrxrdb == uibph2ssmwrp::AUX_DPRIO_READ
auxm_dprio_clkdiv == uibph2ssmwrp::AUXM_CLK_DIVISION_2
auxm_dprio_clken == uibph2ssmwrp::AUXM_CLK_DISABLE
auxm_iocsr_clk_div == uibph2ssmwrp::IOCSR_CLK_DIVISION_2
auxm_iocsr_data == 32'd0
auxm_iocsr_rd_req == uibph2ssmwrp::IOCSR_READ_OFF
auxm_iocsr_wr_req == uibph2ssmwrp::IOCSR_WRITE_OFF
powerdown_mode == uibph2ssmwrp::FALSE
powermode_ac == uibph2ssmwrp::AC_POWERUP
powermode_dc == uibph2ssmwrp::POWERUP
powermode_freq_hz == 32'd1000000
xsstck.a_sup_mode == uibph2sstck::PRODUCTION_MODE
xsstck.a_uib_mode == uibph2sstck::UIB_HBM2E
xsstck.obs_mx2_sel == uibph2sstck::OBS_MUX2_SEL0
xsstck.obs_mx_sel == uibph2sstck::OBS_MUX_SEL0
xsstck.powerdown_mode == uibph2sstck::FALSE
xsstck.powermode_dc == uibph2sstck::POWERUP
xsstck.xaux.powerdown_mode == uibph2sstck_aux_wrap::FALSE
xsstck.xaux.powermode_dc == uibph2sstck_aux_wrap::POWERUP
xsstck.xaux.sup_mode == uibph2sstck_aux_wrap::PRODUCTION_MODE
xsstck.xaux.u_aux_custom_blk.ioauxmaster_p5v_vref_trim == aux_custom_top::P5V_VREF_TRIM_6
xsstck.xaux.u_aux_custom_blk.ioauxmaster_sel_fusetrim_ramtrim_p5v == aux_custom_top::SEL_RAMTRIM
xsstck.xaux.u_aux_custom_blk.ioauxmaster_tstmux_statreg == aux_custom_top::IOAUXMASTER_TSTMUX_STATREG_0
xsstck.xaux.u_aux_custom_blk.powerdown_mode == aux_custom_top::TRUE
xsstck.xaux.u_aux_custom_blk.powermode_dc == aux_custom_top::POWERDOWN
xsstck.xaux.u_aux_custom_blk.sup_mode == aux_custom_top::USER_MODE
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_atb_en == aux_atb::ATB_GLOBAL_DISABLE
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_atbcmp_pdb == aux_atb::ATB_COMP_POWER_DOWN
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_atben0 == aux_atb::ATBEN0_DISABLE
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_atben0_io == aux_atb::ATB0_PRECOMP_OPEN
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_atben0_swap == aux_atb::ATBEN0_SWAP_DISABLE
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_atben1 == aux_atb::ATBEN1_DISABLE
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_atben1_io == aux_atb::ATB1_PRECOMP_OPEN
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_atben1_swap == aux_atb::ATBEN1_SWAP_DISABLE
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_comp_minus == aux_atb::ATB_COMP_MINUS_DISCONNECT
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_comp_plus == aux_atb::ATB_COMP_PLUS_DISCONNECT
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_vgen_sel == 7'd64
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_vgen_selvcca == aux_atb::VREF_COMP_VCCA_DISCONNECT
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_vgen_selvref == aux_atb::VREF_COMP_VCCEREF_DISCONNECT
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_vrefen_minus == aux_atb::VREF_COMP_MINUS_DISCONNECT
xsstck.xaux.u_aux_custom_blk.xatb.ioauxmaster_vrefen_plus == aux_atb::VREF_COMP_PLUS_DISCONNECT
xsstck.xaux.u_aux_custom_blk.xatb.powerdown_mode == aux_atb::FALSE
xsstck.xaux.u_aux_custom_blk.xrefgen.ioauxmaster_atb_mode == aux_refgen_small::ATB_DEFAULT
xsstck.xaux.u_aux_custom_blk.xrefgen.ioauxmaster_bg_powerdown == aux_refgen_small::IOAUXMASTER_BG_POWER_DOWN
xsstck.xaux.u_aux_custom_blk.xrefgen.ioauxmaster_bypass_vcceref_to_irefc == aux_refgen_small::IOAUXMASTER_NORMAL_OPERATION_FOR_IREFC
xsstck.xaux.u_aux_custom_blk.xrefgen.ioauxmaster_iconstant_opt == aux_refgen_small::ICONSTANT_OPT_50U
xsstck.xaux.u_aux_custom_blk.xrefgen.powerdown_mode == aux_refgen_small::FALSE
xsstck.xaux.xdprio.cfg_dprio_sel_core == uibph2sstck_aux_dprio::AVALON_ACCESS_FROM_CORE
xsstck.xaux.xdprio.dprio_base_addr == 9'd0
xsstck.xaux.xdprio.dprio_broadcast_en == uibph2sstck_aux_dprio::DPRIO_BROADCAST_EN_CSR_CTRL_DISABLE
xsstck.xaux.xdprio.dprio_cvp_mdio_dis == uibph2sstck_aux_dprio::DPRIO_CVP_MDIO_DIS_CSR_CTRL_DISABLE
xsstck.xaux.xdprio.dprio_force_mdio_dis == uibph2sstck_aux_dprio::DPRIO_FORCE_MDIO_DIS_CSR_CTRL_DISABLE
xsstck.xaux.xdprio.dprio_power_iso_en == uibph2sstck_aux_dprio::DPRIO_POWER_ISO_EN_CSR_CTRL_DISABLE
xsstck.xaux.xdprio.extra_csr == 2'd0
xsstck.xaux.xdprio.powerdown_mode == uibph2sstck_aux_dprio::FALSE
xsstck.xaux.xdprio.uc_channel_base_addr == 8'd0
xsstck.xoutbuf_top.a_sup_mode == uibph2ioreu_outbuf_top::PRODUCTION_MODE
xsstck.xoutbuf_top.a_uib_mode == uibph2ioreu_outbuf_top::UIB_HBM2E
xsstck.xoutbuf_top.outbuf_eqdelay == 6'd0
xsstck.xoutbuf_top.outbuf_ffvsxhicode == 4'd0
xsstck.xoutbuf_top.outbuf_mux_sel == uibph2ioreu_outbuf_top::OUTBUF_MUX_SEL0
xsstck.xoutbuf_top.outbuf_pd_ctrl == uibph2ioreu_outbuf_top::PULLDN_SETTING0
xsstck.xoutbuf_top.outbuf_pdb == uibph2ioreu_outbuf_top::DIS_OBSERVE_SIG
xsstck.xoutbuf_top.outbuf_pu_ctrl == uibph2ioreu_outbuf_top::PULLUP_SETTING0
xsstck.xoutbuf_top.outbuf_stateqen == uibph2ioreu_outbuf_top::EQ_LEG4_DCDCAL
xsstck.xoutbuf_top.outbuf_tco_comp_ctrl == 6'd0
xsstck.xoutbuf_top.powerdown_mode == uibph2ioreu_outbuf_top::FALSE
xsstck.xvsshicomptop_wrap.a_sup_mode == uibph2sstck_vsshicomptop_wrap::PRODUCTION_MODE
xsstck.xvsshicomptop_wrap.a_uib_mode == uibph2sstck_vsshicomptop_wrap::UIB_HBM2E
xsstck.xvsshicomptop_wrap.powerdown_mode == uibph2sstck_vsshicomptop_wrap::FALSE
xsstck.xvsshicomptop_wrap.vcomp_bit_loc_ovrd == 9'd0
xsstck.xvsshicomptop_wrap.vcomp_cal_mode == uibph2sstck_vsshicomptop_wrap::DISABLE
xsstck.xvsshicomptop_wrap.vcomp_clr_sticky_stat == uibph2sstck_vsshicomptop_wrap::DISABLE
xsstck.xvsshicomptop_wrap.vcomp_comp_init == uibph2sstck_vsshicomptop_wrap::DISABLE
xsstck.xvsshicomptop_wrap.vcomp_compcodeswitchdelay == 7'd127
xsstck.xvsshicomptop_wrap.vcomp_compsigneden == uibph2sstck_vsshicomptop_wrap::DISABLE
xsstck.xvsshicomptop_wrap.vcomp_compstageswitchdelay == 9'd511
xsstck.xvsshicomptop_wrap.vcomp_data_clk_div == uibph2sstck_vsshicomptop_wrap::DIV_2
xsstck.xvsshicomptop_wrap.vcomp_fsm_reset == uibph2sstck_vsshicomptop_wrap::DISABLE
xsstck.xvsshicomptop_wrap.vcomp_fsm_stage_byp == 9'd0
xsstck.xvsshicomptop_wrap.vcomp_lcc_binstartpos == 5'd16
xsstck.xvsshicomptop_wrap.vcomp_lcc_code_ovrd == 5'd0
xsstck.xvsshicomptop_wrap.vcomp_lcc_code_ovrd_en == uibph2sstck_vsshicomptop_wrap::DISABLE
xsstck.xvsshicomptop_wrap.vcomp_lcc_fsmstartcode == 5'd16
xsstck.xvsshicomptop_wrap.vcomp_leak_binstartpos == 7'd64
xsstck.xvsshicomptop_wrap.vcomp_leak_code_ovrd == 7'd32
xsstck.xvsshicomptop_wrap.vcomp_leak_code_ovrd_en == uibph2sstck_vsshicomptop_wrap::DISABLE
xsstck.xvsshicomptop_wrap.vcomp_leak_fsmstartcode == 7'd64
xsstck.xvsshicomptop_wrap.vcomp_rcomp_code_pd == 6'd0
xsstck.xvsshicomptop_wrap.vcomp_rcomp_code_pu0 == 6'd0
xsstck.xvsshicomptop_wrap.vcomp_rcomp_code_pu1 == 6'd0
xsstck.xvsshicomptop_wrap.vcomp_rcomp_code_pu2 == 6'd0
xsstck.xvsshicomptop_wrap.vcomp_rcomp_code_pu3 == 6'd0
xsstck.xvsshicomptop_wrap.vcomp_rcomp_code_pu4 == 6'd0
xsstck.xvsshicomptop_wrap.vcomp_rcomp_code_pu5 == 6'd0
xsstck.xvsshicomptop_wrap.vcomp_rcomp_code_pu6 == 6'd0
xsstck.xvsshicomptop_wrap.vcomp_rcomp_code_pu7 == 6'd0
xsstck.xvsshicomptop_wrap.vcomp_sinstepbinen == uibph2sstck_vsshicomptop_wrap::DISABLE
xsstck.xvsshicomptop_wrap.vcomp_sinstepresumebin == uibph2sstck_vsshicomptop_wrap::SINSTEPRESUMEBIN_ZERO
xsstck.xvsshicomptop_wrap.vcomp_swcap_vrefen == uibph2sstck_vsshicomptop_wrap::DISABLE
xsstck.xvsshicomptop_wrap.vcomp_timeout_wait_val == 8'd0
xsstck.xvsshicomptop_wrap.vcomp_tx_dcc_sel == 6'd0
xsstck.xvsshicomptop_wrap.xvsshicomptop.a_sup_mode == uibph2ioreu_vsshicomptop::PRODUCTION_MODE
xsstck.xvsshicomptop_wrap.xvsshicomptop.a_uib_mode == uibph2ioreu_vsshicomptop::UIB_HBM2E
xsstck.xvsshicomptop_wrap.xvsshicomptop.atbsel == uibph2ioreu_vsshicomptop::ATB_SETTING0
xsstck.xvsshicomptop_wrap.xvsshicomptop.biascur_ctrl == uibph2ioreu_vsshicomptop::BIASCUR_50UA
xsstck.xvsshicomptop_wrap.xvsshicomptop.i_bwctrl == uibph2ioreu_vsshicomptop::BW_CTRL_4MA
xsstck.xvsshicomptop_wrap.xvsshicomptop.i_modesel == uibph2ioreu_vsshicomptop::MODE_3
xsstck.xvsshicomptop_wrap.xvsshicomptop.i_vrefsel == 9'd249
xsstck.xvsshicomptop_wrap.xvsshicomptop.powerdown_mode == uibph2ioreu_vsshicomptop::FALSE
xsstck.xvsshicomptop_wrap.xvsshicomptop.shunt_glob_vsshi_en == uibph2ioreu_vsshicomptop::DISABLE_SHUNT_GLOB
xsstck.xvsshicomptop_wrap.xvsshicomptop.shunt_vsh_en == uibph2ioreu_vsshicomptop::DISABLE_SHUNT
