m255
K4
z2
!s11f vlog 2025.2 2025.05, May 31 2025
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 d/home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor
valtera_s10_user_rst_clkgate
!s106 Intel
2../../ip/ed_sim/ed_sim_post_configuration_reset_release/altera_s10_user_rst_clkgate_1949/sim/altera_s10_user_rst_clkgate.sv
DXx6 sv_std 3 std 0 22 @5XbY]_OacJl=`ToSm<M^0
!s110 1777055423
!i10b 1
!s100 4H4;jTObgC4MGhlCLlk730
IoFOziZk:@GS@a0R0X]YOO0
S1
R0
w1777055305
8../../ip/ed_sim/ed_sim_post_configuration_reset_release/altera_s10_user_rst_clkgate_1949/sim/altera_s10_user_rst_clkgate.sv
F../../ip/ed_sim/ed_sim_post_configuration_reset_release/altera_s10_user_rst_clkgate_1949/sim/altera_s10_user_rst_clkgate.sv
!i122 0
L0 15 13
VDg1SIo80bB@j0V0VzS_@n1
OL;L;2025.2;82
r1
!s85 0
31
!s108 1777055423.000000
!s107 ../../ip/ed_sim/ed_sim_post_configuration_reset_release/altera_s10_user_rst_clkgate_1949/sim/altera_s10_user_rst_clkgate.sv|
!s90 -reportprogress|300|-sv|-suppress|13338|../../ip/ed_sim/ed_sim_post_configuration_reset_release/altera_s10_user_rst_clkgate_1949/sim/altera_s10_user_rst_clkgate.sv|-work|./libraries/altera_s10_user_rst_clkgate_1949|-statslog|./libraries/stats_log|-csession=incr|-csessiondir|./libraries/sessions|
!i113 0
o-suppress 13338 -sv -work ./libraries/altera_s10_user_rst_clkgate_1949 -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
tCvgOpt 0
