1 13 ddrphy_params 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 655360 0 3798 0
1 24 iocompblock_comp_mem_pkg 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 0 23 0
1 33 tennm_agilex7_io96_ncrypt_sv_unit 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 8 0
1 13 verbosity_pkg 4 fast 155 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_common_sv_packages 0 0 131072 0 193 0
1 26 tennm_atoms_ncrypt_sv_unit 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1048576 0 7887 0
1 30 uibph2sstck_ddrphy_params__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 0 3798 0
1 27 uibssm_dfd_hub_package__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 114 0
1 23 uibssm_lib_package__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 0 1086 0
1 23 ace5_lite_bfm_types_pkg 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 131072 0 223 0
1 30 ace5_lite_operations_class_pkg 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 393216 131072 2232 0
1 20 altera_lnsim_sv_unit 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 0 0
1 24 tennm_noc_simulation_pkg 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 0 345 0
1 25 hydra_mem_axi4_driver_pkg 4 fast 155 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_common_sv_packages 0 0 0 0 295 0
1 21 hydra_rtl_library_pkg 4 fast 155 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_common_sv_packages 0 0 131072 0 205 0
1 22 altera_lnsim_functions 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 393216 0 2648 0
1 35 hydra_mem_axi4_driver_csr_interface 5 synth 155 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/hydra_driver_mem_axi4_100 0 0 0 0 0 0
1 24 tennm_noc_axi_trans_q_if 5 synth 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 0 0 0
1 16 tennm_noc_axi_if 5 synth 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 0 0 0
1 20 ioplltop_dprio_alias 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 393216 655360 2347 0
1 16 ioplltop_coutbuf 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 24 0
1 20 ioplltop_coutbuf_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 43 0
1 21 ioplltop_fblvdsoutbuf 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 43 0
1 25 ioplltop_fblvdsoutbuf_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 71 0
1 19 ioplltop_pllcoutbuf 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 110 0
1 23 ioplltop_pllcoutbuf_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 156 0
1 18 ioplltop_so_ss_buf 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 7 0
1 15 ioplltop_pll_so 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 560 0
1 19 ioplltop_pll_so_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 600 0
1 22 ioplltop_fine_dly_del5 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 491 0
1 22 ioplltop_fine_dly_wrap 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 515 0
1 15 ioplltop_dcaana 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 50 0
1 19 ioplltop_dcaana_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 115 0
1 15 ioplltop_dllout 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 79 0
1 15 ioplltop_extclk 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 158 0
1 19 ioplltop_extclk_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 192 0
1 14 ioplltop_phmux 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 311 0
1 12 ioplltop_cnt 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 391 0
1 13 ioplltop_mcnt 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 1311 0
1 17 ioplltop_mcnt_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 1396 0
1 20 ioplltop_atb_mux4to1 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 103 0
1 16 ioplltop_ldo_aip 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 333 0
1 16 ioplltop_ldo_cbb 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 412 0
1 23 ioplltop_vreg_20ma_wrap 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 491 0
1 27 ioplltop_vreg_20ma_wrap_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 537 0
1 19 ioplltop_vcocal_mux 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 13 0
1 20 ioplltop_vco_cal_cnt 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 215 0
1 24 ioplltop_vco_cal_cnt_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 243 0
1 20 ioplltop_core_lsbank 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 631 0
1 21 ioplltop_dec4to16_ehv 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 200 0
1 18 ioplltop_atb_iopll 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 480 0
1 22 ioplltop_atb_iopll_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 523 0
1 16 ioplltop_testmux 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 140 0
1 20 ioplltop_testmux_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 231 0
1 16 ioplltop_ref_dig 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 96 0
1 19 ioplltop_ref_dig_hs 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 321 0
1 12 ioplltop_ref 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 450 0
1 16 ioplltop_ref_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 460 0
1 13 ioplltop_ncnt 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 424 0
1 17 ioplltop_ncnt_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 450 0
1 23 ioplltop_fine_dly_wrap1 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 514 0
1 15 ioplltop_fb_dig 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 96 0
1 18 ioplltop_fb_dig_hs 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 912 0
1 11 ioplltop_fb 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 1065 0
1 15 ioplltop_fb_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 1099 0
1 28 io756ddgckadccore_adc_clkdiv 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 143 0
1 29 io756ddgckadccore_adc_iclkdrv 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 30 0
1 29 io756ddgckadccore_adc_prbsgen 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 154 0
1 26 io756ddgckadccore_sdmodana 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 109 0
1 20 io756ddgckadccore_ls 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 94 0
1 27 io756ddgckadccore_adcdigtop 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 130 0
1 32 io756ddgckadccore_adcfreezelogic 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 61 0
1 33 io756ddgckadccore_tsadcsdmod10top 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 963 0
1 22 ioplltop_adcsdmod10top 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 1033 0
1 26 ioplltop_adcsdmod10top_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 1115 0
1 14 ioplltop_iref1 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 42 0
1 20 ioplltop_srlpftop_pg 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 39 0
1 15 ioplltop_spetdc 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 269 0
1 28 ioplltop_shr_thm2bin_15bto4b 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 263 0
1 17 ioplltop_spe_meas 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 691 0
1 15 ioplltop_pfd_cp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 891 0
1 17 ioplltop_chgpmplf 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 1418 0
1 21 ioplltop_chgpmplf_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 1603 0
1 21 ioplltop_startup_rdac 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 33 0
1 17 ioplltop_vco_core 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 364 0
1 15 ioplltop_clkgen 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 602 0
1 12 ioplltop_VCO 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 1155 0
1 16 ioplltop_vco_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 262144 655360 1297 0
1 20 ioplltop_pllljtopana 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 393216 655360 3200 0
1 25 ctech_lib_doublesync_rstb 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 64 0
1 16 altr_hps_bitsync 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 171 0
1 24 ioplltop_gdivclkphdelana 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 20 0
1 14 ioplltop_gdiv9 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 425 0
1 14 ioplltop_fbgen 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 810 0
1 18 ioplltop_fbgen_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 882 0
1 13 ioplltop_core 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 1048576 655360 9941 0
1 25 ioplltop_pll_dcstop_logic 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 74 0
1 22 uibph2ioetcpll_se2diff 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 13 0
1 25 uibph2ioetcpll_dcc_muxsel 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 50 0
1 21 uibph2ioetcpll_dcc_in 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 75 0
1 27 uibph2ioetcpll_coarse_inout 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 13 0
1 33 uibph2ioetcpll_slv_dcc_mindly_inv 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 30 0
1 36 uibph2ioetcpll_gray2therm_decode_x72 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 156 0
1 43 uibph2ioetcpll_coarse_control_logic_x72_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 70 0
1 32 uibph2ioetcpll_interp_thermo_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 13 0
1 40 uibph2ioetcpll_coarse_control_noninv_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 60 0
1 37 uibph2ioetcpll_coarse_control_inv_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 64 0
1 37 uibph2ioetcpll_coarse_control_sub_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 524288 655360 607 0
1 36 uibph2ioetcpll_coarse_control_72_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 3276800 655360 4078 0
1 22 uibph2ioetcpll_dlycell 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 134 0
1 26 uibph2ioetcpll_dlycell_odd 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 111 0
1 25 uibph2ioetcpll_dlycell_x8 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 1163 0
1 26 uibph2ioetcpll_dlycell_x72 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 7246 0
1 33 uibph2ioetcpll_coarse_dly_x72_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 3276800 655360 11391 0
1 36 uibph2ioetcpll_gray2therm_decode_x16 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 44 0
1 40 uibph2ioetcpll_interp_control_thermo_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 245 0
1 40 uibph2ioetcpll_interp_onehot_presetb_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 20 0
1 32 uibph2ioetcpll_interp_onehot_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 30 0
1 40 uibph2ioetcpll_interp_control_onehot_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 289 0
1 33 uibph2ioetcpll_interp_control_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 262144 655360 1214 0
1 31 uibph2ioetcpll_interp_coarsedly 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 7 0
1 21 uibph2ioetcpll_interp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 393216 655360 2612 0
1 27 uibph2ioetcpll_fine_dly_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 655360 655360 3886 0
1 26 uibph2ioetcpll_dlyline_byp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 4063232 655360 15355 0
1 29 uibph2ioetcpll_phase_detector 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 54 0
1 32 uibph2ioetcpll_slv_dcc_logic_out 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 76 0
1 22 uibph2ioetcpll_slv_dcc 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 4063232 655360 15774 0
1 19 ioplltop_pll_dcstop 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 4063232 655360 16050 0
1 23 ioplltop_pll_dcstop_wrp 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 4063232 655360 16159 0
1 15 ioplltop_custom 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 6946816 655360 44953 0
1 16 altr_hps_ckmux21 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 13 0
1 13 altr_hps_ckor 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 10 0
1 19 altr_hps_ckand_gate 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 10 0
1 27 iopllwrap_fpll_pulldown_pll 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 21 0
1 22 cdclib_rst_n_sync_core 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 77 0
1 18 ctech_lib_mux_2to1 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 13 0
1 21 cdclib_rst_n_sync_dft 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 114 0
1 14 altr_hps_ckinv 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 8 0
1 19 altr_hps_te_clkgate 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 26 0
1 22 iopllwrap_fpll_selfrst 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 328 0
1 23 iopllwrap_fpll_ctrl_cnt 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 157 0
1 13 iopllwrap_dps 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 494 0
1 20 cfg_cmn_non_scan_reg 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 12 0
1 13 cfg_cmn_latch 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 15 0
1 8 cfg_bead 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 65 0
1 13 cfg_cmn_latch 7 fast__1 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 15 0
1 8 cfg_bead 7 fast__1 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 65 0
1 20 iocfgshared_bead_bus 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 4054 0
1 22 iocfgshared_av_readmux 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 199 0
1 23 iocfgshared_avbb_decode 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 262144 655360 1974 0
1 17 iocfgshared_av2bb 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 2412 0
1 20 iocfgshared_bead_bus 7 fast__1 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 67430 0
1 17 iocfgshared_av2bb 7 fast__1 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 2412 0
1 22 iocfgshared_av_bb_rdwr 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 524288 655360 122870 0
1 21 iocfgshared_cmn_latch 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 38 0
1 22 iopllwrap_bb_avmm_wrap 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 786432 655360 128494 0
1 17 altr_hps_bitsync4 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 412 0
1 14 altr_hps_mux21 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 13 0
1 18 altr_hps_rstnsync4 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 476 0
1 14 altr_hps_mux41 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 24 0
1 23 iopllwrap_dcc_sequencer 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 859 0
1 17 iopllwrap_b2g3bit 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 24 0
1 17 iopllwrap_b2g7bit 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 39 0
1 17 iopllwrap_slv_dly 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 262144 655360 2385 0
1 14 altr_hps_ckand 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 10 0
1 16 altr_hps_bitsync 7 fast__1 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 171 0
1 27 iopllwrap_slv_dcc_meas_base 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 714 0
1 23 iopllwrap_bin2gray_conv 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 131072 655360 917 0
1 17 iopllwrap_slv_dcc 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 393216 655360 3751 0
1 17 iopllwrap_dcc_top 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 786432 655360 8066 0
1 19 iopllwrap_fpll_ctrl 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 1966080 655360 140840 0
1 12 iopllwrap_bf 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 9043968 655360 186666 0
1 23 io96b_sim_control_block 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 173 0
1 28 fp8_iopllwrap_bf_init_tieoff 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 0 655360 489 0
1 25 tennm_ph2_iopll_encrypted 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 5505024 655360 24826 0
1 15 tennm_ph2_iopll 4 fast 72 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm_agilex7_io96 0 0 5636096 0 25318 0
1 41 ed_sim_core_pll_altera_iopll_2100_rqn467i 4 fast 147 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_iopll_2100 0 0 5636096 0 25416 0
1 15 ed_sim_core_pll 4 fast 145 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_core_pll 0 0 5636096 0 25432 0
1 26 altera_avalon_clock_source 4 fast 160 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_avalon_clock_source_191 0 0 0 131072 104 0
1 29 ed_sim_core_pll_refclk_source 4 fast 159 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_core_pll_refclk_source 0 0 0 0 112 0
1 25 altera_reset_synchronizer 4 fast 158 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_reset_controller_1924 0 0 0 0 134 0
1 25 altera_reset_synchronizer 7 fast__1 158 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_reset_controller_1924 0 0 0 0 134 0
1 23 altera_reset_controller 4 fast 158 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_reset_controller_1924 0 0 131072 0 816 0
1 27 ed_sim_csr_reset_controller 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_csr_reset_controller 0 0 131072 0 998 0
1 32 intel_mem_ip_reset_fanout_helper 4 fast 166 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/intel_mem_ip_reset_fanout_helper_110 0 0 131072 0 297 0
1 75 ed_sim_csr_reset_fanout_helper_intel_mem_ip_reset_fanout_helper_110_36uzpwq 4 fast 166 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/intel_mem_ip_reset_fanout_helper_110 0 0 131072 0 424 0
1 30 ed_sim_csr_reset_fanout_helper 4 fast 160 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_csr_reset_fanout_helper 0 0 131072 0 551 0
1 17 mem_reset_handler 4 fast 151 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/mem_reset_handler_100 0 0 0 0 333 0
1 63 ed_sim_global_user_reset_extender_mem_reset_handler_100_gumipxa 4 fast 151 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/mem_reset_handler_100 0 0 0 0 476 0
1 33 ed_sim_global_user_reset_extender 4 fast 163 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_global_user_reset_extender 0 0 0 0 610 0
1 62 ed_sim_global_user_reset_handler_mem_reset_handler_100_l46t7qi 4 fast 151 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/mem_reset_handler_100 0 0 0 0 476 0
1 32 ed_sim_global_user_reset_handler 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_global_user_reset_handler 0 0 131072 0 610 0
1 26 altera_avalon_reset_source 4 fast 160 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_avalon_reset_source_191 0 0 0 131072 99 0
1 31 ed_sim_global_user_reset_source 4 fast 161 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_global_user_reset_source 0 0 0 0 110 0
1 20 aliasd_m13_w240__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 21 ijtag_sib_type_1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 104 0
1 14 ijtag_tdr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 141 0
1 27 uibph2ioreu_outbuf_dcc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 69 0
1 42 uibph2ioreu_tx_viewtxtop_interface_ls__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 226 0
1 26 uibph2ioreu_tx_tcodec__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 172 0
1 30 uibph2ioreu_tx_3to8dec_wp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 93 0
1 30 uibph2ioreu_tx_scomplogic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 153 0
1 32 uibph2ioreu_tx_3bitthermdec__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 106 0
1 30 uibph2ioreu_shrd_dcacell0__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 319 0
1 28 uibph2ioreu_shrd_dcaana__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 688 0
1 40 uibph2ioreu_tx_roslewdelaycell_r40p__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 112 0
1 29 uibph2ioreu_shrd_hvlsana__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 10 0
1 36 uibph2ioreu_tx_matchedhvlsdelay__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 30 uibph2ioreu_tx_fsinv_54pp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 38 0
1 35 uibph2ioreu_tx_lvdxrx_vbiasgen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 314 0
1 38 uibph2ioreu_tx_predrvctrl_central__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 649 0
1 33 uibph2ioreu_tx_atpg_xor_60pp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 41 0
1 29 uibph2ioreu_tx_txsegment__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 772 0
1 28 uibph2ioreu_tx_txafetop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 2583 0
1 35 uibph2ioreu_tx_viewvccana_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 9 0
1 29 uibph2ioreu_tx_viewtxana__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3774 0
1 29 uibph2ioreu_tx_viewtxtop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 4539 0
1 37 uibph2ioetc_localvccgen_psio_sub__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 68 0
1 33 uibph2ioetc_localvccgen_psio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 93 0
1 33 uibph2ioetc_s3localvccgen_sw__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 4 0
1 27 uibph2ioreu_outbuf_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 3407872 1048576 23761 0
1 30 ctech_lib_doublesync_rstb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 64 0
1 27 cdclib_rst_n_sync_core__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 77 0
1 23 ctech_lib_mux_2to1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 13 0
1 26 cdclib_rst_n_sync_dft__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 114 0
1 29 uibph2ioreu_vsshi_op_amp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 54 0
1 30 uibph2ioreu_shrd_atpg_xor__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 41 0
1 33 uibph2ioreu_vsshi_lvlshifter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 423 0
1 42 uibph2ioreu_vref_vrefinttop_interface__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 42 0
1 33 uibph2ioreu_vref_r2rhvladder__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 158 0
1 30 uibph2ioreu_vref_atpg_xor__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 59 0
1 32 uibph2ioreu_vref_vrefinttop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 416 0
1 38 uibph2ioreu_vsshi_vrefinttop_wrap__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 444 0
1 35 uibph2ioreu_vsshi_opamptop_m14__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1045 0
1 30 uibph2ioreu_vsshiopamptop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1127 0
1 37 uibph2ioreu_shrd_swcap_3phclkgen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 122 0
1 30 uibph2ioreu_shrd_rcomp_ls__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 10 0
1 33 uibph2ioreu_shrd_rcompampana__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 92 0
1 36 uibph2ioreu_shrd_rcompampclkgen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 56 0
1 30 uibph2ioreu_shrd_rcompamp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 206 0
1 34 uibph2ioreu_shrd_swcapcompana__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 246 0
1 36 uibph2ioreu_shrd_scapcompmodule__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 566 0
1 28 uibph2ioetc_vsshiff_vcc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 34 0
1 22 uibph2io_psio_dft__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 76 0
1 23 uibph2io_ctrl_wrap__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 157 0
1 25 uibph2io_tx_code_buf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 75 0
1 26 uibph2io_tx_preoutstg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 286 0
1 25 uibph2io_txpreoutdrv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 856 0
1 20 uibph2ioetc_atb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 91 0
1 29 uibph2ioreu_vsshicomptop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 2993 0
1 21 altr_hps_clkgate__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 22 0
1 33 uibph2sstck_vsshicomptop_fsm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2111 0
1 25 uibph2sstck_iobinfsm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1703936 614 0
1 25 uibph2sstck_iobinfsm__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1703936 614 0
1 21 altr_hps_ckmux41__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 32 0
1 24 uibph2sstck_div_clk__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 92 0
1 21 altr_hps_bitsync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 171 0
1 21 altr_hps_bitsync__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 835 0
1 21 altr_hps_bitsync__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 752 0
1 21 altr_hps_bitsync__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 669 0
1 21 altr_hps_bitsync__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 503 0
1 21 altr_hps_bitsync__fp8 7 fast__5 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 586 0
1 34 uibph2sstck_vsshicomptop_wrap__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 21825 0
1 21 aliasv_gm0_w1620__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 5 0
1 20 aliasv_m14_w378__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 5 0
1 21 altr_hps_bitsync__fp8 7 fast__6 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 752 0
1 32 uibph2sstck_aux_clkmux_cell__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 13 0
1 20 cfg_cmn_clk_mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 13 0
1 25 cfg_cmn_non_scan_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 12 0
1 27 cfg_dprio_ctrl_reg_bit__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 61 0
1 25 cfg_cmn_non_scan_reg__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 12 0
1 27 cfg_dprio_ctrl_reg_bit__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 61 0
1 29 cfg_dprio_ctrl_reg_nbits__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 775 0
1 29 cfg_dprio_ctrl_reg_nbits__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 775 0
1 29 cfg_dprio_ctrl_reg_nbits__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 775 0
1 29 cfg_dprio_ctrl_reg_nbits__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 775 0
1 29 cfg_dprio_ctrl_reg_nbits__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 775 0
1 29 cfg_dprio_ctrl_reg_nbits__fp8 7 fast__5 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 775 0
1 29 cfg_dprio_ctrl_reg_nregs__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 8257536 1048576 6254 0
1 20 cdclib_bitsync2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 156 0
1 31 cfg_dprio_status_sync_regs__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 290 0
1 31 cfg_dprio_status_reg_nbits__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 57 0
1 31 cfg_dprio_status_reg_nregs__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 551 0
1 27 cfg_dprio_readdata_sel__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 21 0
1 27 cfg_dprio_readdata_mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1128 0
1 33 cfg_dprio_ctrl_stat_reg_chnl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 8388608 1048576 8822 0
1 26 cfg_dprio_csr_reg_bit__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 34 0
1 28 cfg_dprio_csr_reg_nbits__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 410 0
1 28 cfg_dprio_csr_reg_nregs__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1408 0
1 32 cfg_dprio_ctrl_stat_reg_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 8650752 1048576 10898 0
1 33 cfg_dprio_shadow_status_regs__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 210 0
1 34 cfg_dprio_shadow_status_nregs__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 329 0
1 26 uibph2sstck_aux_dprio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 8781824 1048576 12339 0
1 15 aux_rambuf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 125 0
1 25 aux_dec3to7thermo_hv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 47 0
1 21 aux_dec4to16_ehv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 200 0
1 25 aux_vreftrim_mux2to1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 9 0
1 26 aux_refgen_ctrl_small__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 545 0
1 21 aux_refgen_small__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 852 0
1 21 aux_dec7to128_hv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 523 0
1 17 aux_atb_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 556 0
1 12 aux_atb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 756 0
1 19 aux_custom_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1960 0
1 25 uibph2sstck_aux_wrap__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 9043968 1048576 14500 0
1 19 altr_hps_ckinv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 24 altr_hps_clkgate_or__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 21 0
1 19 altr_hps_ckand__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 10 0
1 21 altr_hps_ckmux21__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 13 0
1 21 altr_hps_bitsync__fp8 7 fast__7 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 171 0
1 22 altr_hps_bitsync4__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 412 0
1 19 altr_hps_mux21__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 13 0
1 22 altr_hps_rstnsync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 235 0
1 21 occ_enable_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 878 0
1 20 uibph2sstck_ntl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1183 0
1 23 aesd_asic_d1d4_m10__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 9 0
1 28 uibph2ioetc_pwrgood_inv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 16 uibph2sstck__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 13893632 1048576 63635 0
1 23 uibssm_axi_prepend__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 815 0
1 26 test_control_register__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 25 0
1 25 dft_clock_controller__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1072 0
1 23 uibssm_occ_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1123 0
1 31 uibssm_uibsubsys_atpg_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 9555 0
1 19 altr_hps_gtiel__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 4 0
1 14 uibssm_bs__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 148 0
1 18 uibssm_calbus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 345 0
1 14 ijtag_tdr__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 141 0
1 24 altr_hps_te_clkgate__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 26 0
1 30 uibssm_ijtag_beadbus_ovrd__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 267 0
1 30 uibssm_ijtag_beadbus_ovrd__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 267 0
1 28 uibssm_ijtag_iocsr_ovrd__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 148 0
1 28 uibssm_ijtag_iocsr_ovrd__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 148 0
1 30 uibssm_ijtag_beadbus_ovrd__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 267 0
1 14 ijtag_tdr__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 141 0
1 14 ijtag_tdr__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 141 0
1 21 uibssm_dft_ijtag__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1048576 1048576 6146 0
1 59 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_NNNNNNNLC_XBUF__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 64 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_NNNNNNNLC_NOTIF_BUF__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 58 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_NNNNNNNLC_BUF__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 61 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_NNNNNNNLC_MUX2_1__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 58 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_NNNNNNNLC_CAN__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 62 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_NNNNNNNLC_LATCH_P__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 62 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_NNNNNNNLC_LATCH_N__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 63 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_NNNNNNNLC_DFF_SCAN__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 62 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_NNNNNNNLC_DFF_RST__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 48 ip756uhdsp11rf_1024x39m4b1wd_nnnnnnnlc_gbio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2560 0
1 49 ip756uhdsp11rf_1024x39m4b1wd_nnnnnnnlc_array__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1093 0
1 43 ip756uhdsp11rf_1024x39m4b1wd_nnnnnnnlc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1572864 1048576 13146 0
1 37 uibssm_dfd_ram_rtl_tessent_sib_1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 300 0
1 37 uibssm_dfd_ram_rtl_tessent_sib_2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 105 0
1 17 altr_hps_buf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 44 uibssm_dfd_ram_rtl_tessent_tdr_sri_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 129 0
1 37 uibssm_dfd_ram_rtl_tessent_sib_3__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 105 0
1 45 uibssm_dfd_ram_rtl_tessent_mbist_bap_tdr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 555 0
1 45 uibssm_dfd_ram_rtl_tessent_mbist_bap_sib__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 95 0
1 41 uibssm_dfd_ram_rtl_tessent_mbist_bap__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 912 0
1 25 altr_hps_rst_bitsync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 176 0
1 17 altr_hps_and__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 10 0
1 69 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_async_interf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 341 0
1 63 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_option__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 488 0
1 60 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_fsm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 275 0
1 70 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_pointer_cntrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 8781824 1048576 13532 0
1 64 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_add_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 2753 0
1 67 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_add_format__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 14 0
1 67 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_signal_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 5430 0
1 69 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_delaycounter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 233 0
1 65 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_data_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 837 0
1 74 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_repeat_loop_cntrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1835008 1048576 16559 0
1 66 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_counter_a__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 284 0
1 65 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller_ctl_comp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 718 0
1 56 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_controller__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 13369344 1048576 43881 0
1 67 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_interface_MEM1_STATUS__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1380 0
1 60 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_interface_MEM1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2857 0
1 67 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_interface_MEM2_STATUS__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1380 0
1 60 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_interface_MEM2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2857 0
1 67 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_interface_MEM3_STATUS__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1380 0
1 60 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_interface_MEM3__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2857 0
1 67 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_interface_MEM4_STATUS__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1380 0
1 60 uibssm_dfd_ram_rtl_tessent_mbist_SRAM_c1_interface_MEM4__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2857 0
1 53 uibssm_dfd_ram_rtl_tessent_mbist_diagnosis_ready__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 151 0
1 28 uibssm_dfd_aryfrz_macro__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 47 0
1 19 uibssm_dfd_ram__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 14811136 1048576 58265 0
1 21 altr_hps_bitsync__fp8 7 fast__8 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 171 0
1 23 uibssm_dfd_bitsync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 331 0
1 26 uibssm_dfd_hub_csrgen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1869 0
1 21 altr_hps_bitsync__fp8 7 fast__9 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 254 0
1 21 altr_hps_bitsync__fp8 8 fast__10 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 752 0
1 23 uibssm_dfd_bitsync__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1269 0
1 19 uibssm_dfd_mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2621440 1310720 22958 0
1 20 uibssm_dfd_trig__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1310720 2657 0
1 26 uibssm_dfd_bus_dcsync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 777 0
1 26 uibssm_dfd_bus_dcsync__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 777 0
1 26 uibssm_dfd_bus_dcsync__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 777 0
1 28 uibssm_dfd_mst_avmm_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 4339 0
1 21 uibssm_dfd_trace__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 382 0
1 19 uibssm_dfd_hub__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 3932160 1310720 35327 0
1 15 uibssm_dfd__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 4063232 1310720 36001 0
1 45 altera_avalon_encrypted_st_pipeline_base__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 280 0
1 45 altera_avalon_encrypted_st_pipeline_base__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 280 0
1 45 altera_avalon_encrypted_st_pipeline_base__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 280 0
1 45 altera_avalon_encrypted_st_pipeline_base__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 280 0
1 22 altera_axi_bridge__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 3563 0
1 31 uibssm_axi_pipeline_bridge__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3794 0
1 26 uibssm_uibss_dft_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1282 0
1 18 cfg_cmn_latch__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 15 0
1 13 cfg_bead__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 65 0
1 27 cfg_bead_bus_periphery__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7861 0
1 24 cfgdeccalbus_clkbuf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 25 cfgdeccalbus_clkgate__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 29 0
1 20 cfgdeccalbus_ep__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 330 0
1 17 cfgdeccalbus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2719 0
1 21 altr_hps_bitsync__fp8 8 fast__11 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 918 0
1 20 uibssm_auxm_mmr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1071 0
1 19 altr_hps_ckbuf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 29 uibssm_auxm_iocsr_bridge__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 494 0
1 20 uibssm_auxm_cdc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 28 0
1 29 uibssm_auxm_dprio_clkdiv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 213 0
1 29 uibssm_auxm_dprio_bridge__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 269 0
1 20 uibssm_auxm_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 16079 0
1 24 uibssm_cnt_dft_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 873 0
1 21 cnt_axi4lite_int__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 179 0
1 33 jtag_common_cj_magic_compare__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 39 0
1 25 jtag_common_tap_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 591 0
1 28 jtag_common_cj_tdo_pipe__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 59 0
1 31 jtag_common_cj_tdo_aligner__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 150 0
1 27 jtag_common_tap_dr_tdo__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 46 0
1 30 jtag_common_tap_dr_update__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 54 0
1 29 jtag_common_tap_dr_shift__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 71 0
1 40 jtag_common_tap_dr_shift_update_tdo__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 253 0
1 23 jtag_common_tap_ir__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 315 0
1 29 jtag_common_tap_dr_shift__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 71 0
1 33 jtag_common_tap_dr_shift_tdo__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 174 0
1 29 jtag_common_tap_dr_shift__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 71 0
1 33 jtag_common_tap_dr_shift_tdo__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 174 0
1 23 jtag_common_cj_hub__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 2457 0
1 23 jtag_common_cj_jtl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 3215 0
1 23 jtag_common_cj_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 3518 0
1 19 cnt_cjtag_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 3596 0
1 23 cnt_cjtag_test_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 393 0
1 13 cnt_lpct__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 52 0
1 28 cnt_lpct_clock_gate_and__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 32 0
1 25 cnt_lpct_clock_gater__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 92 0
1 26 test_control_register__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 25 0
1 22 gray_code_counter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 36 0
1 21 occ_enable_logic__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 893 0
1 25 dft_clock_controller__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1051 0
1 17 cnt_clk_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1921 0
1 21 lfsr64_scrambler__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 420 0
1 26 scrambler_descrambler__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 529 0
1 25 cnt_cnoc_descrambler__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 625 0
1 26 cnocif_crc32optimized__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 361 0
1 25 cnt_cnoc_crc_checker__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 445 0
1 24 cnt_cnoc_hdr_insptr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 993 0
1 26 cnt_cnoc_request_unit__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1491 0
1 23 cnt_cnoc_reply_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 477 0
1 22 cnt_cnoc_rx_cntls__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 363 0
1 26 cnt_cnoc_rx_registers__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2384 0
1 23 cnt_cnoc_rx_regtop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2742 0
1 16 cnt_cnoc_rx__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 9174 0
1 26 cnt_cnoc_tx_registers__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 267 0
1 23 cnt_cnoc_tx_regtop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 355 0
1 28 cnt_cnoc_tx_packet_unit__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1131 0
1 22 cnt_cnoc_tx_cntls__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 246 0
1 16 cnt_cnoc_tx__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2246 0
1 25 cnt_edt_decompressor__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1708 0
1 49 cnt_edt_spatial_compactor_22_w_output_lockup__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 200 0
1 49 cnt_edt_spatial_compactor_21_w_output_lockup__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 198 0
1 22 cnt_edt_compactor__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1482 0
1 24 cnt_edt_xor_decoder__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1516 0
1 35 cnt_edt_onehot_decoder_5_to_22__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 58 0
1 35 cnt_edt_onehot_decoder_5_to_21__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 56 0
1 23 cnt_edt_controller__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2361 0
1 25 cnt_edt_bypass_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1270 0
1 12 cnt_edt__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 6881 0
1 33 uibssm_bf_cpu_cpu_test_bench__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 2663 0
1 43 uibssm_bf_cpu_cpu_register_bank_module__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1447 0
1 38 uibssm_bf_cpu_cpu_nios2_oci_debug__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 305 0
1 38 uibssm_bf_cpu_cpu_nios2_oci_break__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 661 0
1 37 uibssm_bf_cpu_cpu_nios2_oci_xbrk__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 441 0
1 37 uibssm_bf_cpu_cpu_nios2_oci_dbrk__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 416 0
1 39 uibssm_bf_cpu_cpu_nios2_oci_itrace__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 377 0
1 40 uibssm_bf_cpu_cpu_nios2_oci_td_mode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 39 0
1 39 uibssm_bf_cpu_cpu_nios2_oci_dtrace__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 112 0
1 53 uibssm_bf_cpu_cpu_nios2_oci_compute_input_tm_cnt__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 44 0
1 47 uibssm_bf_cpu_cpu_nios2_oci_fifo_wrptr_inc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 34 0
1 45 uibssm_bf_cpu_cpu_nios2_oci_fifo_cnt_inc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 43 0
1 37 uibssm_bf_cpu_cpu_nios2_oci_fifo__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1416 0
1 36 uibssm_bf_cpu_cpu_nios2_oci_pib__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 4 0
1 35 uibssm_bf_cpu_cpu_nios2_oci_im__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 52 0
1 57 uibssm_bf_cpu_cpu_nios2_oci_debug_host_slave_control__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 981 0
1 32 uibssm_bf_cpu_cpu_nios2_oci__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 5362 0
1 22 uibssm_bf_cpu_cpu__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 5373952 1048576 36491 0
1 18 uibssm_bf_cpu__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 5373952 1048576 36636 0
1 38 altera_avalon_encrypted_mm_bridge__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 759 0
1 24 cnt_dbg_test_jtagsm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 259 0
1 22 cnt_dbg_test_atpg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 34 0
1 28 cnt_dbg_test_cnoc_route__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 134 0
1 20 cnt_dbg_test_id__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 52 0
1 16 altr_hps_or__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 10 0
1 23 cnt_dbg_test_secen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 147 0
1 23 cnt_dbg_test_tdoen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 87 0
1 24 cnt_dbg_test_arscan__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 108 0
1 24 cnt_dbg_test_bypass__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 52 0
1 25 cnt_dbg_test_sigread__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 130 0
1 26 cnt_dbg_test_sdm_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 142 0
1 24 cnt_dbg_test_pinmux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 85 0
1 28 cnt_dbg_test_dfx_bypass__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 45 0
1 26 cnt_dbg_test_adpt_rst__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 45 0
1 31 cnt_dbg_test_wkpullup_ovrd__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 45 0
1 26 cnt_dbg_test_mbist_en__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 33 0
1 28 cnt_dbg_test_osc_mon_en__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 33 0
1 31 cnt_dbg_test_proc_mon_t2_0__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 33 0
1 31 cnt_dbg_test_proc_mon_t2_1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 33 0
1 31 cnt_dbg_test_proc_mon_t2_2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 33 0
1 31 cnt_dbg_test_proc_mon_t2_3__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 33 0
1 29 cnt_dbg_test_proc_mon_ro__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 33 0
1 31 cnt_dbg_test_3vto1p8v_ovrd__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 45 0
1 31 cnt_dbg_test_tap_clk_gates__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 36 0
1 33 cnt_dbg_test_bscan_clk_gates__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 36 0
1 23 cnt_dbg_test_bscan__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 459 0
1 30 cnt_dbg_test_bscan_auxaib__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 415 0
1 30 cnt_dbg_test_pmarefclk_en__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 45 0
1 28 cnt_dbg_test_async_ovrd__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 94 0
1 32 cnt_dbg_test_tdf_saf_select__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 45 0
1 32 cnt_dbg_test_global_pipe_se__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 45 0
1 27 cnt_dbg_test_tstclksel__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 56 0
1 22 cnt_dbg_test_hvqk__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 636 0
1 32 cnt_dbg_test_tdo_pipe_align__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 210 0
1 21 cnt_dbg_test_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 4527 0
1 29 uibssm_bf_dfd_secure_pio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 53 0
1 32 uibssm_bf_dma_read_data_mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 141 0
1 30 uibssm_bf_dma_byteenables__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 47 0
1 13 fifo_ram__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 366 0
1 16 fifo_module__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 671 0
1 27 uibssm_bf_dma_mem_read__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 165 0
1 28 uibssm_bf_dma_mem_write__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 31 0
1 18 uibssm_bf_dma__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1889 0
1 28 altera_std_synchronizer__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 229 0
1 35 altera_std_synchronizer_bundle__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 256 0
1 29 altera_irq_clock_crosser__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 294 0
1 34 uibssm_bf_hbmc_irq_port_split__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 50 0
1 26 ctech_lib_clk_gate_te__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 28 0
1 32 icf_idvp_ctrl_stap_data_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 195 0
1 21 icf_idvp_counter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 490 0
1 22 ctech_lib_clk_buf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 11 0
1 28 icf_idvp_fublet_control__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 558 0
1 22 ctech_lib_clk_and__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 10 0
1 27 ctech_lib_clk_mux_2to1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 13 0
1 29 icf_idvp_cnt_freq_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 442 0
1 22 icf_idvp_stap_fsm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1076 0
1 24 icf_idvp_stap_irreg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 172 0
1 26 icf_idvp_stap_decoder__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 90 0
1 26 icf_idvp_stap_decoder__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 90 0
1 26 icf_idvp_stap_decoder__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 90 0
1 26 icf_idvp_stap_decoder__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 90 0
1 26 icf_idvp_stap_decoder__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 90 0
1 26 icf_idvp_stap_decoder__fp8 7 fast__5 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 90 0
1 28 icf_idvp_stap_irdecoder__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1145 0
1 27 icf_idvp_stap_data_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 195 0
1 34 icf_idvp_stap_remote_data_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 19 0
1 24 icf_idvp_stap_drreg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2261 0
1 25 icf_idvp_stap_tdomux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 121 0
1 23 icf_idvp_stap_glue__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 279 0
1 35 icf_idvp_stap_dfxsecure_plugin__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 459 0
1 18 icf_idvp_stap__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 917504 1048576 6542 0
1 21 icf_idvp_tdo_mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 99 0
1 24 icf_idvp_controller__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1572864 1048576 9742 0
1 21 cnt_iocsr_bridge__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 765 0
1 21 cnt_iocsr_bridge__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 849 0
1 22 altera_irq_bridge__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 211 0
1 38 altera_avalon_encrypted_mm_bridge__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 759 0
1 38 altera_avalon_encrypted_mm_bridge__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 582 0
1 20 uibssm_bf_pio_0__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 53 0
1 20 uibssm_bf_pio_1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 53 0
1 20 uibssm_bf_pio_2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 53 0
1 24 cnt_ram_byte_modify__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 44 0
1 16 cnt_ram_rmw__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 456 0
1 29 uibssm_bist_cnt_ram_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1572 0
1 18 altr_hps_and3__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 14 0
1 20 ecc_ccr_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 328 0
1 16 ecc_ram_rmw__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1128 0
1 21 ecc_imam_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1739 0
1 21 ecc_intr_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 613 0
1 20 ecc_lut_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 633 0
1 11 ecc_cb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 14 0
1 11 ecc_cb__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 14 0
1 12 ecc_pcm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1048576 1048576 1470 0
1 12 ecc_enc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1048576 1048576 1540 0
1 14 ecc_sv_32__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 76 0
1 12 ecc_dec__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1048576 1048576 1772 0
1 16 ecc_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2359296 1048576 4847 0
1 17 altr_hps_xor__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 10 0
1 59 INTC_MEMIP_IP756UHDSP11RF_2048X39M4B2WD_CNNNNNNLC_XBUF__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 64 INTC_MEMIP_IP756UHDSP11RF_2048X39M4B2WD_CNNNNNNLC_NOTIF_BUF__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 58 INTC_MEMIP_IP756UHDSP11RF_2048X39M4B2WD_CNNNNNNLC_BUF__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 61 INTC_MEMIP_IP756UHDSP11RF_2048X39M4B2WD_CNNNNNNLC_MUX2_1__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 58 INTC_MEMIP_IP756UHDSP11RF_2048X39M4B2WD_CNNNNNNLC_CAN__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 62 INTC_MEMIP_IP756UHDSP11RF_2048X39M4B2WD_CNNNNNNLC_LATCH_P__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 62 INTC_MEMIP_IP756UHDSP11RF_2048X39M4B2WD_CNNNNNNLC_LATCH_N__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 63 INTC_MEMIP_IP756UHDSP11RF_2048X39M4B2WD_CNNNNNNLC_DFF_SCAN__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 62 INTC_MEMIP_IP756UHDSP11RF_2048X39M4B2WD_CNNNNNNLC_DFF_RST__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 48 ip756uhdsp11rf_2048x39m4b2wd_cnnnnnnlc_gbio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2560 0
1 49 ip756uhdsp11rf_2048x39m4b2wd_cnnnnnnlc_array__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1097 0
1 43 ip756uhdsp11rf_2048x39m4b2wd_cnnnnnnlc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1572864 1048576 13433 0
1 61 uibssm_bf_CLK250MHz_MBIST1_LVISION_MBISTPG_RETIMING_CELL__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 191 0
1 61 uibssm_bf_CLK250MHz_MBIST1_LVISION_MEM1_INTERFACE_STATUS__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2331 0
1 79 uibssm_bf_CLK250MHz_MBIST1_LVISION_MEM1_INTERFACE_ColumnRedundancyAnalysis__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 576 0
1 76 uibssm_bf_CLK250MHz_MBIST1_LVISION_MEM1_INTERFACE_RowRedundancyAnalysis__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 17 0
1 54 uibssm_bf_CLK250MHz_MBIST1_LVISION_MEM1_INTERFACE__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 5126 0
1 34 uibssm_bist_spram_uib_ssm_ram__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 12058624 1048576 160919 0
1 18 spram_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 754 0
1 17 sram_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 243 0
1 32 uibssm_bist_uib_ssm_ecc_ram__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 15073280 1048576 171410 0
1 26 cnt_ram_ctrlreg_slave__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 238 0
1 26 uibssm_bist_cnt_ram_1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 15597568 1048576 175909 0
1 31 cnt_rst_ctrl_reset_req_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 205 0
1 31 cnt_rst_ctrl_reset_req_gen__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 205 0
1 17 cnt_rst_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 3670 0
1 22 cnt_mesosync_fifo__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1003 0
1 20 cnt_rx_test_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 2150 0
1 25 uibssm_bf_secure_pio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 70 0
1 23 cnt_serctrl_avalmm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1034 0
1 31 cnt_serctrl_clkgate_serial__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 32 0
1 29 cnt_serctrl_clkgate_conv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 36 0
1 27 cnt_serctrl_clkcounter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 52 0
1 21 cnt_serctrl_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 855 0
1 24 cnt_serctrl_p2sns2p__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1820 0
1 20 cnt_serctrl_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 4033 0
1 37 uibssm_bf_serial_ctrl_port_split__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 118 0
1 38 altera_avalon_encrypted_sld2mm_dr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 247 0
1 28 altera_std_synchronizer__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 229 0
1 46 altera_avalon_encrypted_sld2mm_tck_domain__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 817 0
1 46 altera_avalon_encrypted_sld2mm_sys_domain__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 1197 0
1 35 altera_avalon_encrypted_sld2mm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 917504 1048576 2409 0
1 27 uibssm_atpg_rst_export__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 28 uibssm_rst_port_conduit__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 16 0
1 22 cnt_sys_test_ckor__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 38 0
1 24 cnt_sys_test_clkgen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 587 0
1 35 cnt_sys_test_peripheral_slvint__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1568 0
1 29 cnt_sys_test_main_slvint__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 274 0
1 24 cnt_sys_test_regmap__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 54 0
1 22 cnt_sys_test_lfsr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3239 0
1 27 cnt_sys_test_atpg_lfsr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3938 0
1 27 cnt_sys_test_signature__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 4544 0
1 24 cnt_sys_test_regmap__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 54 0
1 27 cnt_sys_test_ipcounter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 5083 0
1 24 cnt_sys_test_regmap__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 54 0
1 24 cnt_sys_test_regmap__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 54 0
1 25 cnt_sys_test_ctrlreg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1268 0
1 26 cnt_sys_test_debugreg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 187 0
1 29 cnt_sys_test_security_en__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 18 0
1 21 cnt_sys_test_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1048576 1048576 14177 0
1 21 uibssm_bf_timer0__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 359 0
1 20 cnt_tx_test_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 423 0
1 29 uibssm_avmm_err_response__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 113 0
1 25 uibssm_cal_ctrl_fifo__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 956 0
1 25 uibssm_cal_ctrl_fifo__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 987 0
1 27 uibssm_cal_ctrl_bridge__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2520 0
1 18 altr_hps_ckor__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 10 0
1 20 uibssm_cal_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3320 0
1 16 cnt_ram_rmw__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 456 0
1 29 uibssm_bist_cnt_ram_ctrl__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1572 0
1 16 ecc_ram_rmw__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1128 0
1 21 ecc_imam_wrapper__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1739 0
1 21 ecc_intr_wrapper__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 613 0
1 20 ecc_lut_wrapper__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 633 0
1 59 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_CNNNNNNLC_XBUF__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 64 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_CNNNNNNLC_NOTIF_BUF__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 58 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_CNNNNNNLC_BUF__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 61 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_CNNNNNNLC_MUX2_1__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 58 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_CNNNNNNLC_CAN__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 62 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_CNNNNNNLC_LATCH_P__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 62 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_CNNNNNNLC_LATCH_N__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 63 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_CNNNNNNLC_DFF_SCAN__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 62 INTC_MEMIP_IP756UHDSP11RF_1024X39M4B1WD_CNNNNNNLC_DFF_RST__fp8 7 verilog 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 0 0 0
1 48 ip756uhdsp11rf_1024x39m4b1wd_cnnnnnnlc_gbio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2560 0
1 49 ip756uhdsp11rf_1024x39m4b1wd_cnnnnnnlc_array__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1093 0
1 43 ip756uhdsp11rf_1024x39m4b1wd_cnnnnnnlc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1572864 1048576 13380 0
1 62 uibssm_bf_CLK250MHz_MBIST1_LVISION_MEM17_INTERFACE_STATUS__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2331 0
1 80 uibssm_bf_CLK250MHz_MBIST1_LVISION_MEM17_INTERFACE_ColumnRedundancyAnalysis__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 576 0
1 77 uibssm_bf_CLK250MHz_MBIST1_LVISION_MEM17_INTERFACE_RowRedundancyAnalysis__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 17 0
1 55 uibssm_bf_CLK250MHz_MBIST1_LVISION_MEM17_INTERFACE__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 5042 0
1 37 uibssm_bist_spram_uib_ssm_ur_ram__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 6289 0
1 18 spram_wrapper__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 754 0
1 17 sram_wrapper__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 243 0
1 35 uibssm_bist_uib_ssm_ur_ecc_ram__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 3670016 1048576 15986 0
1 24 uibssm_bist_cnt_ram__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 4194304 1048576 19071 0
1 26 altera_vic_output_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 23 0
1 26 altera_vic_config_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 119 0
1 29 altera_vic_reg_set_clear__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 55 0
1 22 altera_vic_reg_ro__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 30 0
1 19 altera_vic_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 37 0
1 22 altera_vic_reg_ro__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 30 0
1 19 altera_vic_reg__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 37 0
1 19 altera_vic_csr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 5601 0
1 24 altera_vic_compare4__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 349 0
1 24 altera_vic_compare2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 171 0
1 24 altera_vic_priority__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 4756 0
1 22 altera_vic_vector__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 198 0
1 18 uibssm_bf_vic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 10867 0
1 46 altera_merlin_encrypted_master_translator__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1160 0
1 46 altera_merlin_encrypted_master_translator__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1160 0
1 46 altera_merlin_encrypted_master_translator__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1160 0
1 46 altera_merlin_encrypted_master_translator__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1160 0
1 46 altera_merlin_encrypted_master_translator__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1160 0
1 46 altera_merlin_encrypted_master_translator__fp8 7 fast__5 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1160 0
1 46 altera_merlin_encrypted_master_translator__fp8 7 fast__6 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1160 0
1 45 altera_merlin_encrypted_slave_translator__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 7 fast__5 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 7 fast__6 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 7 fast__7 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 7 fast__8 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 7 fast__9 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 8 fast__10 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 45 altera_merlin_encrypted_slave_translator__fp8 8 fast__11 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1062 0
1 42 altera_merlin_encrypted_axi_master_ni__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1976 0
1 41 altera_merlin_encrypted_master_agent__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 665 0
1 41 altera_merlin_encrypted_master_agent__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 665 0
1 41 altera_merlin_encrypted_master_agent__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 665 0
1 41 altera_merlin_encrypted_master_agent__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 665 0
1 41 altera_merlin_encrypted_master_agent__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 665 0
1 41 altera_merlin_encrypted_master_agent__fp8 7 fast__5 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 665 0
1 41 altera_merlin_encrypted_master_agent__fp8 7 fast__6 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 665 0
1 47 altera_merlin_encrypted_burst_uncompressor__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 478 0
1 40 altera_merlin_encrypted_slave_agent__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2068 0
1 36 altera_avalon_encrypted_sc_fifo__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2509 0
1 36 altera_avalon_encrypted_sc_fifo__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1945 0
1 36 altera_avalon_encrypted_sc_fifo__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1987 0
1 36 altera_avalon_encrypted_sc_fifo__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1986 0
1 54 uibssm_bf_mm_interconnect_0_router_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 58 0
1 39 uibssm_bf_mm_interconnect_0_router__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 233 0
1 58 uibssm_bf_mm_interconnect_0_router_002_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 58 0
1 43 uibssm_bf_mm_interconnect_0_router_002__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 329 0
1 58 uibssm_bf_mm_interconnect_0_router_003_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 58 0
1 43 uibssm_bf_mm_interconnect_0_router_003__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 344 0
1 58 uibssm_bf_mm_interconnect_0_router_004_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 58 0
1 43 uibssm_bf_mm_interconnect_0_router_004__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 246 0
1 58 uibssm_bf_mm_interconnect_0_router_005_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 58 0
1 43 uibssm_bf_mm_interconnect_0_router_005__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 321 0
1 58 uibssm_bf_mm_interconnect_0_router_006_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 58 0
1 43 uibssm_bf_mm_interconnect_0_router_006__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 269 0
1 58 uibssm_bf_mm_interconnect_0_router_007_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 58 0
1 43 uibssm_bf_mm_interconnect_0_router_007__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 208 0
1 58 uibssm_bf_mm_interconnect_0_router_009_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 60 0
1 43 uibssm_bf_mm_interconnect_0_router_009__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 244 0
1 58 uibssm_bf_mm_interconnect_0_router_010_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 60 0
1 43 uibssm_bf_mm_interconnect_0_router_010__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 217 0
1 58 uibssm_bf_mm_interconnect_0_router_011_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 58 0
1 43 uibssm_bf_mm_interconnect_0_router_011__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 236 0
1 58 uibssm_bf_mm_interconnect_0_router_012_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 58 0
1 43 uibssm_bf_mm_interconnect_0_router_012__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 210 0
1 58 uibssm_bf_mm_interconnect_0_router_013_default_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 58 0
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1 40 uibssm_bf_mm_interconnect_2_cmd_mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 53 0
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1 33 uibssm_bf_LVISION_JTAP_STATE__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 826 0
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1 27 uibssm_bf_LVISION_JTAP__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3107 0
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1 51 uibssm_bf_CLK250MHz_MBIST1_LVISION_MBISTPG_FSM__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 260 0
1 61 uibssm_bf_CLK250MHz_MBIST1_LVISION_MBISTPG_POINTER_CNTRL__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 4037 0
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1 58 uibssm_bf_CLK250MHz_MBIST1_LVISION_MBISTPG_ADD_FORMAT__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 21 0
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1 65 uibssm_bf_CLK250MHz_MBIST1_LVISION_MBISTPG_REPEAT_LOOP_CNTRL__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 924 0
1 57 uibssm_bf_CLK250MHz_MBIST1_LVISION_MBISTPG_COUNTER_A__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 164 0
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1 52 uibssm_bf_CLK250MHz_MBIST1_LVISION_MBISTPG_CTRL__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2228224 1048576 16065 0
1 28 uibssm_bf_LV_BGROUP_DEF__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 40 0
1 14 uibssm_bf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 78905344 1048576 650055 0
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1 50 f8xshipmidvslvd2mifm4_f8xsidvnes072222ll22osc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 17 0
1 50 f8xshipmidvslvd2mifm4_f8xsidvnes072222ll22top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 31 0
1 44 f8xshipmidvslvd2mifm4_f8xmidvdsld2ringr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1024 0
1 44 f8xshipmidvslvd2mifm4_f8xmidvdsld2bankr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1260 0
1 42 f8xshipmidvslvd2mifm4_f8xmidvdsld2mif__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 4084 0
1 26 f8xshipmidvslvd2mifm4__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 4166 0
1 17 uibph2ssmwrp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 116785152 1048576 862300 0
1 23 tennm_uib_ssm_encrypted 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 118620160 1048576 871994 0
1 13 tennm_uib_ssm 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 118751232 0 872166 0
1 45 ed_sim_hbm_fp_0_hbm_arch_fp_10_v5kblii_uibssm 4 fast 144 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/hbm_arch_fp_10 0 0 118751232 0 872309 0
1 17 tennm_ph2_io_ibuf 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 0 90 0
1 29 intel_hbmss_ph2_uib_msio_ibuf 4 fast 144 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/hbm_arch_fp_10 0 0 131072 0 123 0
1 29 intel_hbmss_ph2_uib_msio_ibuf 7 fast__1 144 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/hbm_arch_fp_10 0 0 393216 0 317 0
1 25 hbmc_rst_n_sync_core__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 83 0
1 20 hbmc_rst_n_sync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 126 0
1 22 hbmc_clkrst_8xtop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 3696 0
1 30 ctech_lib_doublesync_setb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 64 0
1 21 altr_hps_bitsync__fp8 8 fast__12 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 171 0
1 25 hbmc_uibsts_repeater__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1414 0
1 22 hbmc_hr_phase_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1847 0
1 26 hbmc_cfgdec_pipestage__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 440 0
1 29 hbmc_axilite_ipreg_2chnl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 429 0
1 23 hbmc_axilite_ipreg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 2155 0
1 22 hbmc_clkrst_4xtop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 61 0
1 18 hbmc_scan_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 168 0
1 35 hbmc_4x_edt_rtl1_tessent_sib_1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 103 0
1 35 hbmc_4x_edt_rtl1_tessent_sib_2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 103 0
1 42 hbmc_4x_edt_rtl1_tessent_clk_gate_and__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 39 0
1 33 hbmc_4x_edt_rtl1_tessent_inv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 30 0
1 37 hbmc_4x_edt_rtl1_tessent_clk_buf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 14 0
1 33 hbmc_4x_edt_rtl1_tessent_buf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 14 0
1 59 hbmc_4x_edt_rtl1_tessent_edt_c3_decompressor_segment_1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1477 0
1 59 hbmc_4x_edt_rtl1_tessent_edt_c3_decompressor_segment_2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1465 0
1 59 hbmc_4x_edt_rtl1_tessent_edt_c3_decompressor_segment_3__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1460 0
1 49 hbmc_4x_edt_rtl1_tessent_edt_c3_decompressor__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 4437 0
1 74 hbmc_4x_edt_rtl1_tessent_edt_c3_spatial_compactor_100_w_output_lockup__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 763 0
1 46 hbmc_4x_edt_rtl1_tessent_edt_c3_compactor__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 3106 0
1 60 hbmc_4x_edt_rtl1_tessent_edt_c3_low_power_shift_decoder__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2004 0
1 63 hbmc_4x_edt_rtl1_tessent_edt_c3_low_power_shift_controller__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 5748 0
1 48 hbmc_4x_edt_rtl1_tessent_edt_c3_xor_decoder__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 4010 0
1 60 hbmc_4x_edt_rtl1_tessent_edt_c3_onehot_decoder_7_to_100__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 214 0
1 47 hbmc_4x_edt_rtl1_tessent_edt_c3_controller__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 10956 0
1 49 hbmc_4x_edt_rtl1_tessent_edt_c3_bypass_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3237 0
1 36 hbmc_4x_edt_rtl1_tessent_edt_c3__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2490368 1048576 35605 0
1 40 hbmc_4x_edt_rtl1_tessent_edt_c3_tdr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 136 0
1 16 hbmc_4x_edt__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2490368 1048576 36150 0
1 14 ijtag_tdr__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 141 0
1 21 hbmc_clk_divider__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 33 0
1 16 hbmc_clkrst__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 350 0
1 22 hbmc_clkrst_2xtop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 2220 0
1 18 cfg_cmn_latch__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 15 0
1 13 cfg_bead__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 65 0
1 27 cfg_bead_bus_periphery__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 6597 0
1 23 hbmc_cfgdecbeadbus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 6770 0
1 17 cfgdeccalbus__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3778 0
1 16 hbmc_cfgdec__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 10711 0
1 21 altr_hps_bitsync__fp8 8 fast__13 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 14779 0
1 15 hbmc_mux21__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1217 0
1 15 hbmc_mux21__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 985 0
1 13 hbmc_mmr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2097152 1048576 14761 0
1 19 hbmc_calib_mmr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2490368 1048576 36097 0
1 22 hbmc_stim_gen_chk__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1446 0
1 25 hbmc_axi_skid_buffer__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 145 0
1 25 hbmc_axi_skid_buffer__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 145 0
1 25 hbmc_axi_skid_buffer__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 145 0
1 25 hbmc_axi_skid_buffer__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 145 0
1 16 hbmc_scfifo__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7098 0
1 22 hbmc_axi4_adapter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 14141 0
1 23 hbmc_addr_remapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1225 0
1 18 hbmc_addr_scr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 78 0
1 18 hbmc_addr_map__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3172 0
1 24 hbmc_rcq_dependency__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 6671 0
1 24 hbmc_wcq_dependency__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 6667 0
1 26 hbmc_dependency_check__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 13852 0
1 23 hbmc_onehot_to_bin__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 2299 0
1 24 hbmc_age_dependency__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1184 0
1 15 hbmc_cmd_q__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 8843 0
1 13 hbmc_rcq__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 24702 0
1 16 hbmc_scfifo__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 3658 0
1 16 hbmc_scfifo__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 11226 0
1 15 hbmc_cmd_q__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 8843 0
1 13 hbmc_wcq__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 37460 0
1 32 hbmc_priority_onehot_to_bin__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 2311 0
1 23 hbmc_cmd_scheduler__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 20382 0
1 28 hbmc_starvation_handler__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 3936 0
1 18 hbmc_bank_fsm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 125 0
1 21 hbmc_bank_timers__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2292 0
1 30 hbmc_pseudochannel_timers__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2300 0
1 26 hbmc_bankgroup_timers__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1434 0
1 22 hbmc_stack_timers__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 211 0
1 22 hbmc_color_timers__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 14155776 1048576 101697 0
1 20 hbmc_age_muxsel__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 943 0
1 20 hbmc_age_muxsel__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 4471 0
1 22 hbmc_row_arb_q2bg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 41277 0
1 19 hbmc_rr_muxsel__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 666 0
1 19 hbmc_rr_muxsel__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 396 0
1 19 hbmc_rr_muxsel__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 216 0
1 26 hbmc_rr_onehot_to_bin__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 208 0
1 20 hbmc_row_arb_bg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 2038 0
1 20 hbmc_row_rd_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 4130 0
1 20 hbmc_row_wr_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 4134 0
1 17 hbmc_row_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 9119 0
1 22 hbmc_col_arb_q2bg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 54882 0
1 20 hbmc_col_arb_bg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 2402 0
1 20 hbmc_col_rd_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 4470 0
1 20 hbmc_col_wr_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 4635 0
1 17 hbmc_col_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 11616 0
1 19 hbmc_bank_idle__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 2975 0
1 20 hbmc_color_pipe__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 17694720 1048576 217835 0
1 17 hbmc_swizzle__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1820 0
1 16 hbmc_ph_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 70 0
1 19 hbmc_dctrl_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 283 0
1 19 hbmc_dctrl_gen__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 651 0
1 18 dpram_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1424 0
1 17 dram_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 449 0
1 23 ecc_ccr_wrapper_2p__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 596 0
1 16 ecc_ram_rmw__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1128 0
1 21 ecc_imam_wrapper__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1739 0
1 21 ecc_intr_wrapper__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 613 0
1 20 ecc_lut_wrapper__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 633 0
1 11 ecc_cb__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 14 0
1 12 ecc_pcm__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 1712 0
1 12 ecc_enc__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 1782 0
1 14 ecc_sv_64__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 140 0
1 12 ecc_dec__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 2078 0
1 16 ecc_wrapper__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2621440 1048576 5395 0
1 55 ip756hs2p11rf_128x72m1b2wd_cnnnnnnnl_lock_up_latch__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 25 0
1 41 ip756hs2p11rf_128x72m1b2wd_cnnnnnnnl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 6214 0
1 71 hbmc_pseudo_channel_rtl_tessent_mbist_RF_c1_interface_MEM14_STATUS__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 3719 0
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1 22 hbmc_aryfrz_macro__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 47 0
1 24 hbmc_pseudo_channel__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 21889024 1048576 310764 0
1 22 hbmc_color_timers__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 14155776 1048576 101697 0
1 17 hbmc_col_arb__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 11616 0
1 20 hbmc_color_pipe__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 17694720 1048576 217835 0
1 24 hbmc_data_scrambler__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 2102 0
1 25 hbmc_write_data_ctrl__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 12604 0
1 24 hbmc_data_scrambler__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 2088 0
1 24 hbmc_read_data_ctrl__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 42427 0
1 24 hbmc_pseudo_channel__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 21889024 1048576 310764 0
1 24 hbmc_master_row_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 429 0
1 24 hbmc_master_col_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 48 0
1 20 hbmc_master_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 619 0
1 24 hbmc_channel_timers__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 354 0
1 17 hbmc_par_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 82 0
1 21 hbmc_row_cmd_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 644 0
1 21 hbmc_row_cmd_gen__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 644 0
1 20 hbmc_outph_adpt__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 283 0
1 17 hbmc_par_gen__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 82 0
1 21 hbmc_col_cmd_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 297 0
1 21 hbmc_col_cmd_gen__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 297 0
1 20 hbmc_outph_adpt__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 283 0
1 20 hbmc_outph_adpt__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 283 0
1 20 hbmc_outph_adpt__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 283 0
1 20 hbmc_outph_adpt__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 283 0
1 20 hbmc_outph_adpt__fp8 7 fast__5 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 283 0
1 21 hbmc_wrdata_adpt__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 2068 0
1 19 hbmc_inph_adpt__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 329 0
1 19 hbmc_inph_adpt__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 329 0
1 19 hbmc_inph_adpt__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 329 0
1 21 hbmc_rddata_adpt__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 1813 0
1 19 hbmc_inph_adpt__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 329 0
1 24 hbmc_obs_fr_hr_adpt__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 98 0
1 24 hbmc_obs_fr_hr_adpt__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 98 0
1 24 hbmc_obs_fr_hr_adpt__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 98 0
1 24 hbmc_obs_fr_hr_adpt__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 98 0
1 21 hbmc_wufi_gasket__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2228224 1048576 17449 0
1 13 hbmc_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 47185920 1048576 648978 0
1 21 altr_hps_bitsync__fp8 8 fast__14 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 6645 0
1 21 altr_hps_bitsync__fp8 8 fast__15 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1001 0
1 15 hbmc_mux21__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 521 0
1 15 hbmc_mux21__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1594 0
1 15 hbmc_mux21__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 144 0
1 13 hbmc_csr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2752512 1048576 20775 0
1 24 hbmc_csr_rfrsh_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 274 0
1 17 hbmc_csr_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 4325376 1048576 41572 0
1 27 hbmc_hybrid_pbrfsh_fsm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 212 0
1 21 hbmc_bitscan_arb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 21 0
1 28 hbmc_hybrid_pbrfsh_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 10096 0
1 26 hbmc_perbank_rfsh_fsm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 254 0
1 23 hbmc_onehot_to_bin__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1562 0
1 20 hbmc_age_muxsel__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 767 0
1 21 hbmc_pbrfsh_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 14803 0
1 16 hbmc_sb_pch__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1133 0
1 24 hbmc_sb_rfsh_policy__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 3536 0
1 22 hbmc_sb_user_rfsh__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1183 0
1 17 hbmc_sb_rfsh__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1379 0
1 29 hbmc_sb_self_rfsh_policy__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 603 0
1 22 hbmc_sb_self_rfsh__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 899 0
1 30 hbmc_sb_power_down_policy__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 278 0
1 23 hbmc_sb_power_down__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 917 0
1 20 hbmc_sb_arbiter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 2656 0
1 23 hbmc_sb_bank_timer__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 551 0
1 23 hbmc_sb_bank_timer__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 551 0
1 23 hbmc_sb_bank_timer__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 18385 0
1 23 hbmc_sb_bank_timer__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 551 0
1 19 hbmc_sb_common__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1048576 1048576 28804 0
1 21 hbmc_sb_addr_cmd__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1252 0
1 16 hbmc_sb_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 3801088 1048576 138455 0
1 16 hbmc_filter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 339 0
1 16 hbmc_filter__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 699 0
1 16 hbmc_filter__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1419 0
1 26 hbmc_thermal_throttle__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 339 0
1 15 hbmc_1xtop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 57016320 1048576 867552 0
1 22 hbmc_axilite2avmm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 761 0
1 26 hbmc_wufi_ufi_adapter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1835008 1048576 25488 0
1 28 hbmc_wufi_ufi_2xadapter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 3932160 1048576 53811 0
1 15 hbmc_2xtop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 11141120 1048576 149269 0
1 16 hbmc_ub_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 366 0
1 21 hbmc_phy_intf_ps__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 10996 0
1 15 hbmc_4xtop__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 4325376 1048576 54691 0
1 9 hbmc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2097152 1048576 18879 0
1 20 tennm_hbmc_encrypted 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 24166400 1048576 161712 0
1 10 tennm_hbmc 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 25739264 0 170265 0
1 23 uibph2pll_uib_stdf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3878 0
1 24 tennm_uib_stdf_encrypted 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 4096 0
1 14 tennm_uib_stdf 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 0 4167 0
1 19 uibphy_mclkbuf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 278 0
1 24 uibphy_if_ports_grp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 815 0
1 20 uibphy_dft_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 184 0
1 23 uibphy_cfg_wrapper__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 55 0
1 32 uibphy_ub48slice_rst_n_sync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 130 0
1 28 uibphy_ub48slice_mp_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 388 0
1 23 uibphy_two_one_mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 81 0
1 17 uibphy_21mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 25 0
1 39 uibphy_ub48slice_lfsrmisr_bit_psio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 40 0
1 39 uibphy_ub48slice_lfsrmisr_bit_pdio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 48 0
1 43 uibphy_ub48slice_statbuf_lfsrmisr_lane__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1620 0
1 42 uibphy_ub48slice_statbuf_lfsrmisr_grp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 4841 0
1 30 uibphy_ub48slice_syncwait__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 122 0
1 26 uibphy_strm_lc_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 48 0
1 36 uibphy_ub48slice_ob_lp_cnt_lane__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 220 0
1 35 uibphy_ub48slicemgrob_ctl_lane__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 874 0
1 19 altr_hps_mux41__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 24 0
1 24 uibphy_four_one_mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 441 0
1 23 uibphy_two_one_mux__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 265 0
1 25 uibphy_eight_one_mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1249 0
1 24 uibphy_four_one_mux__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 129 0
1 25 uibphy_eight_one_mux__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 441 0
1 24 uibphy_four_one_mux__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 90 0
1 23 uibphy_two_one_mux__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 58 0
1 25 uibphy_eight_one_mux__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 340 0
1 24 uibphy_four_one_mux__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 285 0
1 23 uibphy_two_one_mux__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 173 0
1 25 uibphy_eight_one_mux__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 845 0
1 36 uibphy_ub48slicemgr_ufimux_data__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1247 0
1 37 uibphy_ub48slicemgr_ufimux_ctl_0__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 239 0
1 37 uibphy_ub48slicemgr_ufimux_ctl_1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 125 0
1 39 uibphy_ub48slicemgrob_datapath_grp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 3538944 1048576 13230 0
1 30 uibphy_ub48slicemgrob_grp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 4718592 1048576 15499 0
1 31 uibphy_cfg_rd_timer_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 42 0
1 29 uibphy_ub48slicemgribctl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 589 0
1 24 uibphy_four_one_mux__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 207 0
1 23 uibphy_two_one_mux__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 127 0
1 25 uibphy_eight_one_mux__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 643 0
1 38 uibphy_ub48slicemgribctl_datapath__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2097152 1048576 4426 0
1 38 uibphy_ub48slicemgribdat_datapath__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1578 0
1 26 uibphy_ub48slicemgrib__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2883584 1048576 7381 0
1 24 uibphy_ub48slicemgr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 13369344 1048576 50069 0
1 24 uibphy_four_one_mux__fp8 7 fast__5 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1299 0
1 32 uibphy_ub48slicemmr_readmux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 65446 0
1 24 uibphy_ub48slicemmr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1572864 1048576 74401 0
1 34 uibphy_ub48slicemmr_atpg_gate__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 302 0
1 25 uibphy_ub48slice_ecc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 12 0
1 35 uibphy_ub48slicedbi_comparator__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 147 0
1 29 uibphy_ub48slicedbi_lane__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 679 0
1 24 uibphy_ub48slicedbi__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 2849 0
1 32 uibphy_ub48slice_parity_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 75 0
1 28 uibphy_ub48slice_parity__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 489 0
1 35 uibphy_ub48slice_rx_parity_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 15 0
1 31 uibphy_ub48slice_rx_parity__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 298 0
1 33 uibphy_ub48slice_ecc_dbi_par__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 8661 0
1 27 uibphy_ub48sliceirrdec__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 136 0
1 27 uibphy_ub48sliceirrmux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1003 0
1 28 uibphy_ub48sliceirr_grp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1289 0
1 28 uibphy_ub48sliceirr_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 935 0
1 19 uibphy_regmode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 398 0
1 24 uibphy_ub48sliceirr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 5190 0
1 30 uibphy_ub48slice_mp_lpbck__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 320 0
1 21 uibphy_ub48slice__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 14680064 1048576 67887 0
1 42 uibphy_ub48slice_statbuf_lfsrmisr_grp__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 4841 0
1 38 uibphy_ub48slicemgribdat_datapath__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1578 0
1 26 uibphy_ub48slicemgrib__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2883584 1048576 7381 0
1 24 uibphy_ub48slicemgr__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 13369344 1048576 50069 0
1 28 uibphy_ub48sliceirr_reg__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 778 0
1 24 uibphy_ub48sliceirr__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 5033 0
1 21 uibphy_ub48slice__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 14680064 1048576 67730 0
1 28 uibphy_ufi_adapter_ub48__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 667 0
1 27 cfg_bead_bus_periphery__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 6913 0
1 25 uibphy_cfgdecbeadbus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7092 0
1 17 cfgdeccalbus__fp8 7 fast__2 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1048576 1048576 9073 0
1 34 uibphy_ub48slice_cfgdeccalbus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 9249 0
1 22 uibphy_cfgdecsync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 242 0
1 31 uibphy_cfgdecmmr_atpg_gate__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 191 0
1 29 uibphy_cfgdecmmr_readmux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7092 0
1 21 uibphy_cfgdecmmr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 8191 0
1 18 uibphy_cfgdec__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1441792 1048576 25662 0
1 19 uibphy_ub48m_r__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2097152 1048576 33769 0
1 20 uibphy_3ub48m_r__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 7864320 1048576 110794 0
1 19 uibphy_ub48m_l__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2097152 1048576 33769 0
1 20 uibphy_3ub48m_l__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 7864320 1048576 110440 0
1 33 uibphy_midm_clknrst_rst_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 275 0
1 15 uibphy_cdc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 23 0
1 31 uibphy_midm_clknrst_clkdiv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 305 0
1 24 uibphy_midm_clknrst__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 666 0
1 27 cfg_bead_bus_periphery__fp8 7 fast__3 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 3911 0
1 25 uibphy_midm_cal_bead__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 4042 0
1 29 uibphy_midm_cfgdeccalbus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2813 0
1 30 uibphy_midm_cal_atpg_gate__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 173 0
1 24 uibphy_midm_cal_mmr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 67282 0
1 21 altr_hps_bitsync__fp8 8 fast__16 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 337 0
1 27 uibphy_midm_hbm_insync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 571 0
1 20 uibphy_midm_cal__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 75386 0
1 14 ijtag_tdr__fp8 7 fast__5 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 141 0
1 36 uibphy_midm_ijtag_ieee1500_ovrd__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 181 0
1 27 uibphy_midm_ctrl_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 632 0
1 18 uibphy_clkdly__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 37 0
1 28 uibphy_midm_ctrl_if_reg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 311 0
1 26 uibphy_midm_ctrl_sync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 426 0
1 32 uibphy_midm_ctrl_writesteer__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 249 0
1 31 uibphy_midm_ctrl_readsteer__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 515 0
1 33 uibphy_midm_ctrl_readsteer_0__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 562 0
1 33 uibphy_midm_ctrl_readsteer_1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 562 0
1 33 uibphy_midm_ctrl_readsteer_2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 562 0
1 21 uibphy_midm_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 3718 0
1 32 uibphy_midm_rcomp_cal_tmplt__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 405 0
1 30 uibphy_midm_rcomp_cal_int__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 419 0
1 32 uibphy_midm_rcomp_cal_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2078 0
1 27 uibphy_midm_rcomp_test__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 181 0
1 26 uibphy_midm_rcomp_dig__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2387 0
1 16 uibphy_midm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2097152 1048576 82813 0
1 15 uibphy_ntl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 340 0
1 27 uibphy_ppmlimit_decode__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 26 0
1 19 uibphy_ppm_cnt__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 822 0
1 15 uibphy_ppm__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7629 0
1 11 uibphy__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 20971520 1048576 330524 0
1 23 tennm_uib_phy_encrypted 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 546340864 1048576 4589653 0
1 13 tennm_uib_phy 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 2621440 0 15464 0
1 25 uibph2ioclk_gclk_buf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 28 0
1 23 uibph2ioclk_buf_m8__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 14 0
1 32 uibph2ioclk_gclk_decap_buf4__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 0 0
1 21 uibph2ioclk_buf4__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 28 0
1 26 uibph2ioclk_gclk_buf2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 28 0
1 33 uibph2ioclk_gclk_buf_diff_se__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 36 0
1 20 aliasd_m12_w240__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 34 uibph2iopnr_gclk_clock_buffer__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1758 0
1 18 aliasd_m6_w44__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 19 aliasd_m10_w80__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 18 aliasd_m8_w76__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 28 uibph2iopnr_gclk_m_ft_r__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1456 0
1 29 uibph2iopnr_gclk_m_ft_lr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1456 0
1 28 uibph2iopnr_gclk_m_ft_l__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1456 0
1 20 aliasd_m10_w240__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 28 uibph2iopnr_gclk_mid_ft__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1384 0
1 29 uibph2iopnr_gclk_pl_to_l__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 3993 0
1 29 uibph2iopnr_gclk_pl_to_r__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 3993 0
1 21 uibph2iopnr_gclk__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 8781824 1048576 102633 0
1 32 uibph2sstop_ioedge_mstwrp_r__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 138 0
1 33 uibph2sstop_ioedge_mstwrp_lr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 138 0
1 32 uibph2sstop_ioedge_mstwrp_l__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 138 0
1 30 uibph2sstop_ioedge_ub48_l__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 301 0
1 30 uibph2sstop_ioedge_ub48_r__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 301 0
1 23 uibph2sstop_ioedge__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 6160384 1048576 45960 0
1 31 uibph2iopnr_mst48_bead_bus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8263 0
1 21 altr_hps_bitsync__fp8 8 fast__17 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 171 0
1 40 uibph2iopnr_dll_atech_clkgate_cgc01__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 30 0
1 25 uibph2iopnr_dll_ctrl__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 162 0
1 25 altr_hps_t2_register__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 31 0
1 36 uibph2iopnr_self_lock_assertion__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 682 0
1 25 uibph2iopnr_dll_core__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 2384 0
1 24 uibph2iopnr_dll_pnr__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3387 0
1 27 uibph2iopnr_gry2binary__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 159 0
1 24 uibph2iopnr_mst_dll__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3876 0
1 24 uibph2iopnr_mst_seq__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 339 0
1 22 uibph2iopnr_cdc03__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 28 0
1 24 uibph2iopnr_clk_div__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 116 0
1 25 uibph2iopnr_counter4__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 21 0
1 36 uibph2iopnr_local_rcomp_cal_pup__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 330 0
1 32 uibph2iopnr_local_rcomp_dig__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1033 0
1 22 uibph2iopnr_mst48__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 19134 0
1 27 uibph2ioetc_pwrgood_or__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 10 0
1 22 uibph2iopnr_ckbuf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 22 uibph2iopnr_ckinv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 24 uibph2iopnr_ckmux41__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 23 0
1 24 uibph2iopnr_ckmux21__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 13 0
1 34 uibph2ioetc_local_rcomp_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 115 0
1 29 uibph2ioetc_tx_preoutstg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 286 0
1 28 uibph2ioetc_local_rcomp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 727 0
1 30 uibph2ioetc_mst_flops_sub__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 53 0
1 26 uibph2ioetc_mst_flops__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 157 0
1 30 uibph2ioetcpll_scan_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 31 0
1 34 uibph2ioetc_mimic_lvl_shifter__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 23 0
1 36 uibph2ioetc_rxsenseamp_core_dqs__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 115 0
1 24 uibph2ioetc_pdio_rx__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 324 0
1 26 uibph2ioetc_iomux3to1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 40 0
1 30 uibph2ioetc_mimic_diff_rx__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 454 0
1 33 uibph2ioetc_mimic_prerx_strb__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 39 uibph2ioetc_gray2therm_decode_x144__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 300 0
1 48 uibph2ioetcpll_coarse_control_logic_x72_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 70 0
1 37 uibph2ioetcpll_interp_thermo_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 13 0
1 45 uibph2ioetcpll_coarse_control_noninv_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 60 0
1 42 uibph2ioetcpll_coarse_control_inv_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 64 0
1 42 uibph2ioetcpll_coarse_control_sub_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 607 0
1 39 uibph2ioetc_coarse_control_x72_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 3739 0
1 40 uibph2ioetc_coarse_control_x144_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 8058 0
1 32 uibph2ioetcpll_coarse_inout__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 13 0
1 27 uibph2ioetcpll_dlycell__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 134 0
1 31 uibph2ioetcpll_dlycell_odd__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 111 0
1 30 uibph2ioetcpll_dlycell_x8__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 1163 0
1 33 uibph2ioetc_dlycell_lead_x72__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7077 0
1 29 uibph2ioetc_dlycell_x144__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 14373 0
1 36 uibph2ioetc_coarse_dly_x144_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 22495 0
1 41 uibph2ioetcpll_gray2therm_decode_x16__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 44 0
1 45 uibph2ioetcpll_interp_control_thermo_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 245 0
1 45 uibph2ioetcpll_interp_onehot_presetb_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 20 0
1 37 uibph2ioetcpll_interp_onehot_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 30 0
1 45 uibph2ioetcpll_interp_control_onehot_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 289 0
1 38 uibph2ioetcpll_interp_control_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 1214 0
1 36 uibph2ioetcpll_interp_coarsedly__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 26 uibph2ioetcpll_interp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2612 0
1 32 uibph2ioetcpll_fine_dly_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 655360 1048576 3886 0
1 33 uibph2ioetc_dlyline_x144_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 917504 1048576 26454 0
1 35 uibph2ioetc_mimic_ub48_ptr_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 44 uibph2ioetc_rxsenseamp_ntail_bwctrl_dec__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 110 0
1 35 uibph2ioetc_rxsenseamp_core_dq__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 92 0
1 24 uibph2ioetc_psio_rx__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 293 0
1 28 uibph2ioetc_mimic_se_rx__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 354 0
1 41 uibph2ioetc_ub48_clkmux4to1_na_mimic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 30 uibph2ioetc_dlycell_mimic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 111 0
1 35 uibph2ioetc_mindly_interp_main__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 86 0
1 36 uibph2ioetc_combiner_core_mimic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 54 0
1 30 uibph2ioetc_mindly_interp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 320 0
1 29 uibph2ioetc_mimic_mindly__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 509 0
1 29 uibph2ioetc_mimic_ptrdly__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 33 uibph2ioetc_rx_mimic_combine__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 579 0
1 39 uibph2ioetc_mimic_sio_rxdcc_mindly__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 614 0
1 34 uibph2ioetcpll_phase_detector__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 54 0
1 27 uibph2ioetc_rx_mst_dll__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 28360 0
1 23 uibph2ioetc_mindly__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2844 0
1 28 uibph2ioetc_mst_dly_byp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1310720 1048576 29400 0
1 29 uibph2ioetc_1cyc_mst_dll__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1310720 1048576 29809 0
1 26 uibph2ioetc_ioclk_buf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 39 0
1 28 uibph2ioetc_localvccgen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 262144 1048576 167 0
1 26 uibph2iopnr_mstdllwrp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 4456448 1048576 81374 0
1 32 uibph2iopnr_mstck_bot_ft_tf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 266 0
1 27 cfg_bead_bus_periphery__fp8 7 fast__4 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 5333 0
1 34 uibph2iopnr_mstck_bot_beadbus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 5441 0
1 20 uibph2iopnr_bsc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 107 0
1 21 altr_hps_bitsync__fp8 8 fast__18 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 171 0
1 24 uibph2ioetc_dblsync__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 212 0
1 35 uibph2io_rcomp_logic_floparray__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 524288 1048576 4271 0
1 31 uibph2io_rcomp_logic_thick__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 299 0
1 23 uibph2io_rcomp_pad__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 37 0
1 36 uibph2io_rcomp_default_internal__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 101 0
1 30 uibph2io_rcomp_comparator__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 155 0
1 19 uibph2io_rcomp__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 786432 1048576 5346 0
1 20 uibph2ioetc_mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 57 0
1 25 uibph2ioetc_gclk_buf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 28 0
1 35 uibph2iopnr_mstck_bot_gclk_int__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 170 0
1 28 uibph2io_vreg_vccl_trim__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 22 0
1 22 uibph2io_vreg_drv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 229 0
1 14 ijtag_tdr__fp8 7 fast__6 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 141 0
1 26 uibph2iopnr_mstck_bot__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 917504 1048576 13214 0
1 21 uibph2ioetc_pdet__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 12 0
1 22 uibph2io_gpio_dig__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 112 0
1 22 uibph2io_gpio_dbv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 198 0
1 25 uibph2io_gpio_txanlg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 966 0
1 25 uibph2io_gpio_rxanlg__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 331 0
1 18 uibph2io_gpio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 1628 0
1 32 uibph2iopnr_gpio_x12_ms_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1966080 1048576 21645 0
1 32 uibph2iopnr_gpio_x12_ms_top__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1966080 1048576 21619 0
1 23 uibph2iopnr_ms_bsc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 99 0
1 27 cfg_bead_bus_periphery__fp8 7 fast__5 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 5333 0
1 34 uibph2iopnr_mstck_top_beadbus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 5442 0
1 26 uibph2iopnr_mstck_top__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 4456448 1048576 50349 0
1 42 uibph2iopnr_slv48_tx_dll_pvt_code_gen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 67 0
1 27 cfg_bead_bus_periphery__fp8 7 fast__6 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 15445 0
1 36 uibph2iopnr_slv48_left_bead_bus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 15870 0
1 24 uibph2iopnr_b2g3bit__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 24 0
1 24 uibph2iopnr_b2g7bit__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 39 0
1 24 uibph2iopnr_slv_dly__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2305 0
1 34 uibph2iopnr_slv_dcc_meas_base__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 714 0
1 30 uibph2iopnr_bin2gray_conv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 917 0
1 24 uibph2iopnr_slv_dcc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 3928 0
1 22 uibph2iopnr_21mux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 13 0
1 27 uibph2iopnr_slv48_left__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1572864 1048576 29726 0
1 27 cfg_bead_bus_periphery__fp8 7 fast__7 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 15445 0
1 37 uibph2iopnr_slv48_right_bead_bus__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 15939 0
1 24 uibph2iopnr_slv_dly__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2305 0
1 28 uibph2iopnr_slv48_right__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1966080 1048576 33526 0
1 26 uibph2ioetc_sio_ppmux__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 15 0
1 21 altr_hps_bitsync__fp8 8 fast__19 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 171 0
1 24 uibph2ioetc_dblsync__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 212 0
1 31 uibph2io_psio_tx_logic_bsc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 560 0
1 27 uibph2io_psio_rx_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 63 0
1 17 uibph2io_sio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2589 0
1 18 uibph2io_psio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2786 0
1 18 uibph2io_psio__fp8 7 fast__1 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 393216 1048576 2786 0
1 34 uibph2ioetc_pdio_dbselmux3to1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 38 0
1 25 uibph2io_tx_db_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 349 0
1 26 uibph2io_tx_dbt_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 428 0
1 24 uibph2io_diffrx_bsc__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 88 0
1 26 uibph2io_tx_dbc_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 437 0
1 31 uibph2io_pdio_diffie_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 26 0
1 28 uibph2io_wdqs_age_logic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 156 0
1 18 uibph2io_pdio__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 1179648 1048576 7499 0
1 22 uibph2iopnr_dllen__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 483 0
1 33 uibph2ioetc_d04gin00ld0l0_a0__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 33 uibph2ioetc_d04gin00ld0l0_a1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 28 uibph2ioetc_txstrb_inv4__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 34 uibph2ioetc_txstrb_inv5_mimic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 2 0
1 28 uibph2ioetc_rxstrb_inv1__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 32 uibph2io_ub48_lclk_top_left__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 68 0
1 28 uibph2ioetc_txstrb_inv5__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 35 uibph2io_ub48_lclk_bottom_left__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 61 0
1 28 uibph2ioetc_txstrb_inv3__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 34 uibph2ioetc_txstrb_inv3_mimic__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 2 0
1 28 uibph2ioetc_rxstrb_inv0__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 35 uibph2io_ub48_lclk_center_left__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 51 0
1 27 uibph2ioetc_predll_inv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 24 uibph2ioetc_tri_buf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 10 0
1 30 uibph2ioetc_ub48_ioclk_pd__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 24 uibph2ioetc_dft_buf__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 33 uibph2ioetc_earlyclkout_inv2__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 30 uibph2ioetc_d04gbf00ld0k0__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 7 0
1 32 uibph2ioetc_earlyclkout_inv__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 0 1048576 8 0
1 35 uibph2ioetc_ub48_clkmux4to1_na__fp8 4 fast 59 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/tennm 0 0 131072 1048576 51 0
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1 31 altera_merlin_address_alignment 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 859 0
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1 31 altera_merlin_address_alignment 7 fast__3 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 653 0
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1 31 altera_merlin_address_alignment 7 fast__5 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 653 0
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1 49 axi_2_axilite_altera_mm_interconnect_1920_tfjuqlq 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 6684672 524288 58003 0
1 48 tennm_noc_interconnect_altera_reset_synchronizer 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 134 0
1 48 tennm_noc_interconnect_altera_reset_synchronizer 7 fast__1 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 134 0
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1 13 axi_2_axilite 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 17432576 524288 135640 0
1 22 tennm_noc_interconnect 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 17563648 524288 136395 0
1 30 tennm_noc_dummy_axi4lite_slave 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 131072 524288 473 0
1 24 tennm_noc_axilite_target 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 786432 524288 5914 0
1 44 ed_sim_hbm_fp_0_intel_noc_target_210_wd3glki 4 fast 150 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/intel_noc_target_210 0 0 786432 0 6367 0
1 25 altera_reset_synchronizer 7 fast__2 158 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_reset_controller_1924 0 0 0 0 143 0
1 23 altera_reset_controller 7 fast__1 158 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_reset_controller_1924 0 0 131072 0 825 0
1 35 ed_sim_hbm_fp_0_hbm_fp_1001_vnrnvly 4 fast 141 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/hbm_fp_1001 0 0 21495808 0 162369 0
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1 26 altera_avalon_reset_source 7 fast__1 160 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_avalon_reset_source_191 0 0 0 131072 99 0
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1 17 mem_reset_handler 7 fast__1 151 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/mem_reset_handler_100 0 0 0 0 333 0
1 52 ed_sim_hbm_reset_merge_mem_reset_handler_100_em3qp7i 4 fast 151 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/mem_reset_handler_100 0 0 0 0 476 0
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1 26 altera_avalon_clock_source 7 fast__1 160 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_avalon_clock_source_191 0 0 0 131072 104 0
1 33 ed_sim_noc_clk_ctrl_refclk_source 4 fast 163 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_noc_clk_ctrl_refclk_source 0 0 0 0 112 0
1 13 tennm_noc_pll 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 10 0
1 21 tennm_noc_dummy_slave 7 fast__2 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 131072 524288 1012 0
1 23 tennm_noc_initiator_bfm 7 fast__2 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 262144 524288 2136 0
1 16 tennm_noc_target 7 fast__2 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 524288 524288 4935 0
1 30 tennm_noc_dummy_axi4lite_slave 7 fast__1 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 131072 524288 473 0
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1 20 noc_monitor_reg_bank 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 124 0
1 16 noc_perf_monitor 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 4269 0
1 13 tennm_noc_ssm 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 786432 524288 10306 0
1 20 intel_noc_clock_ctrl 4 fast 154 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/intel_noc_clock_ctrl_211 0 0 917504 0 10436 0
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1 13 add_a_b_s0_s1 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 66 0
1 24 common_28nm_ram_register 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 163 0
1 24 common_28nm_ram_register 7 fast__1 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 163 0
1 22 common_porta_registers 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 588 0
1 27 common_10nm_lutram_register 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 131072 524288 179 0
1 37 common_28nm_mlab_cell_pulse_generator 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 524288 60 0
1 26 common_28nm_mlab_cell_core 4 fast 66 /home/frank/altera_pro/25.3.1/questa_fe/intel/verilog/altera_lnsim 0 0 0 917504 371 0
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1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_fd4nl5q 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_74mzthy 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_qy5uyja 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_khnaati 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_gv4zpca 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1835008 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_4kmnxyi 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_ncas3qi 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_cgr7q6q 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_yzbliey 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_ulqshvq 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_ouag7py 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 65 ed_sim_traffic_generator_altera_merlin_axi_slave_ni_19128_bqrluba 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_slave_ni_19128 0 0 1966080 0 12725 0
1 73 ed_sim_traffic_generator_altera_merlin_router_1921_ccn5l5i_default_decode 4 fast 155 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_router_1921 0 0 0 0 60 0
1 58 ed_sim_traffic_generator_altera_merlin_router_1921_ccn5l5i 4 fast 155 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_router_1921 0 0 131072 0 595 0
1 73 ed_sim_traffic_generator_altera_merlin_router_1921_xvav5gy_default_decode 4 fast 155 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_router_1921 0 0 0 0 58 0
1 58 ed_sim_traffic_generator_altera_merlin_router_1921_xvav5gy 4 fast 155 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_router_1921 0 0 0 0 187 0
1 67 ed_sim_traffic_generator_altera_merlin_traffic_limiter_1921_6hyjguq 4 fast 164 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_traffic_limiter_1921 0 0 393216 0 2661 0
1 65 ed_sim_traffic_generator_altera_merlin_demultiplexer_1921_43pc4ty 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_demultiplexer_1921 0 0 131072 0 1258 0
1 63 ed_sim_traffic_generator_altera_merlin_multiplexer_1922_b3qw5jq 4 fast 160 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_multiplexer_1922 0 0 131072 0 54 0
1 65 ed_sim_traffic_generator_altera_merlin_demultiplexer_1921_saap25q 4 fast 162 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_demultiplexer_1921 0 0 0 0 73 0
1 23 altera_merlin_arb_adder 7 fast__1 160 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_multiplexer_1922 0 0 0 0 131 0
1 24 altera_merlin_arbitrator 7 fast__1 160 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_multiplexer_1922 0 0 131072 0 540 0
1 63 ed_sim_traffic_generator_altera_merlin_multiplexer_1922_ox7yjda 4 fast 160 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_multiplexer_1922 0 0 393216 0 3062 0
1 60 ed_sim_traffic_generator_altera_mm_interconnect_1920_7e5elta 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 45481984 0 284719 0
1 42 ed_sim_traffic_generator_hydra_400_q34dqpa 4 fast 139 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/hydra_400 0 0 623820800 0 2813797 0
1 24 ed_sim_traffic_generator 4 fast 154 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_traffic_generator 0 0 393216 0 1882 0
1 41 ed_sim_traffic_generator_reset_controller 4 fast 171 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_traffic_generator_reset_controller 0 0 262144 0 998 0
1 89 ed_sim_traffic_generator_reset_fanout_helper_intel_mem_ip_reset_fanout_helper_110_36uzpwq 4 fast 166 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/intel_mem_ip_reset_fanout_helper_110 0 0 131072 0 424 0
1 44 ed_sim_traffic_generator_reset_fanout_helper 4 fast 174 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_traffic_generator_reset_fanout_helper 0 0 131072 0 551 0
1 28 ed_sim_uib_pll_refclk_source 4 fast 158 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim_uib_pll_refclk_source 0 0 0 0 112 0
1 48 ed_sim_altera_merlin_axi_translator_1986_4khp5ei 4 fast 163 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_translator_1986 0 0 393216 0 1991 0
1 48 ed_sim_altera_merlin_axi_translator_1986_4khp5ei 7 fast__1 163 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_merlin_axi_translator_1986 0 0 393216 0 1991 0
1 42 ed_sim_altera_mm_interconnect_1920_zjzatva 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_wdxda2y 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_k3shfky 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 1048576 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_hx64kma 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_3p3yp4a 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_vle5vxa 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_jtbzqha 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 1048576 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_hioiemq 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_nouw5qq 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_tpd6kja 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_rdc4n6a 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_pcvu2hq 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_fepkd3q 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_3fycuca 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_jyojndi 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 917504 0 4704 0
1 42 ed_sim_altera_mm_interconnect_1920_xzzb22y 4 fast 157 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/altera_mm_interconnect_1920 0 0 1048576 0 4704 0
1 6 ed_sim 4 fast 136 /home/frank/data/projects/upwork/grandcroix/github/fpga.backup/quartus/llm/ip/hbm_fp_0_example_design/sim/ed_sim/mentor/libraries/ed_sim 0 0 49283072 0 309123 0
