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; Table of Contents ;
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  1. About this file
  2. Outputs of IP generation
  3. Instantiating IP in a Quartus Prime project


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;   1. About this file ;
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   This is the readme file for the 'intel_axi4_ro_wo_converter' IP v25.3.1.
   This will eventually provide a high-level overview of the IP, but for now this is a placeholder.
   
   This file was auto-generated.


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;   2. Outputs of IP generation ;
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   IP generation supports the following output filesets:
   
      Synthesis            - This is the fileset you should use when instantiating the IP in
                             your Quartus Prime project. RTL files in this fileset can be
                             simulated, but your simulator must support SystemVerilog.
                             Simulating the synthesis files yields identical results to
                             simulating the simulation files.
   
      Simulation           - This fileset contains scripts and source files to help you
                             integrate the IP into your simulation project targeting a
                             3rd-party simulator of your choice. If you select VHDL
                             during IP generation, the fileset contains IEEE-encrypted
                             Verilog files that can be used in VHDL-only simulators, such
                             as ModelSim - Intel FPGA edition. All source files in the simulation
                             filesets are functionally equivalent to the synthesis fileset.


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;   3. Instantiating IP in a Quartus Prime project ;
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   If you instantiate the IP as part of a Platform Designer system, follow the Platform Designer
   documentation on how to instantiate the system in a Quartus Prime project.
   
   If the IP was generated as a standalone component, it is sufficient to add
   the generated .qip file from the synthesis fileset to your Quartus Prime project.
   The .qip file allows the Quartus Prime software to locate all the files of
   the IP, including RTL files, SDC files, hex files, and timing scripts. Once the
   .qip file is added, you can instantiate the memory interface in your RTL.


