| enable_example_design_sim_hwtcl |
1 |
| enable_example_design_synth_hwtcl |
1 |
| enable_32bit_address_hwtcl |
0 |
| select_design_example_rtl_lang_hwtcl |
Verilog |
| chosen_devkit_hwtcl |
NONE |
| top_topology_hwtcl |
Gen4 1x16, Interface - 512 bit |
| topology_1x16_mode_hwtcl |
Native Endpoint |
| g4_pld_clkfreq_single_user_hwtcl |
400MHz |
| virtual_sris_enable_en_hwtcl |
0 |
| rtile_debug_toolkit_hwtcl |
0 |
| pipemode_sim_hwtcl |
0 |
| pipemode_sim_for_ed_hwtcl |
1 |
| independent_perst_x16_hwtcl |
0 |
| hssi_ctr_is_cvp_enable_user_hwtcl |
0 |
| hssi_csb_clk_div_b0_hwtcl |
4 |
| core16_enable_power_mgnt_intf_hwtcl |
0 |
| core16_enable_legacy_int_hwtcl |
0 |
| core16_enable_cpl_timeout_hwtcl |
1 |
| core16_enable_prs_event_hwtcl |
0 |
| core16_enable_error_intf_hwtcl |
1 |
| core16_ehp_ctrl0_header_format_hwtcl |
1 |
| core16_ehp_tx_int_msg_cpl_ctrl_cpl_always_grant_hwtcl |
0 |
| core16_aux_pwr_port_hwtcl |
0 |
| core16_enable_multi_func_hwtcl |
0 |
| core16_enable_sriov_hwtcl |
0 |
| core16_pf0_virtio_capability_present_hwtcl |
0 |
| core16_pf0_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf0_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf0_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf0_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf0_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf0_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf0_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf0_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf0_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf0_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf0_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf0_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf0_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf0_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf0_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf0_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf0_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf0_virtio_pciconfig_access_cfg_data_hwtcl |
0 |
| core16_pf0vf_virtio_capability_present_hwtcl |
0 |
| core16_pf0vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf0vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf0vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf0vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf0vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf0vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf0vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf0vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf0vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf0vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf0vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf0vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf0vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf0vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf0vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf1vf_virtio_capability_present_hwtcl |
0 |
| core16_pf1vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf1vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf1vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf1vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf1vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf1vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf1vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf1vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf1vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf1vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf1vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf1vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf1vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf1vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf1vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf2vf_virtio_capability_present_hwtcl |
0 |
| core16_pf2vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf2vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf2vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf2vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf2vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf2vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf2vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf2vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf2vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf2vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf2vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf2vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf2vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf2vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf2vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf3vf_virtio_capability_present_hwtcl |
0 |
| core16_pf3vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf3vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf3vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf3vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf3vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf3vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf3vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf3vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf3vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf3vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf3vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf3vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf3vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf3vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf3vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf4vf_virtio_capability_present_hwtcl |
0 |
| core16_pf4vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf4vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf4vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf4vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf4vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf4vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf4vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf4vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf4vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf4vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf4vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf4vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf4vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf4vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf4vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf4vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf4vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf5vf_virtio_capability_present_hwtcl |
0 |
| core16_pf5vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf5vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf5vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf5vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf5vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf5vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf5vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf5vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf5vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf5vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf5vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf5vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf5vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf5vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf5vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf5vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf5vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf6vf_virtio_capability_present_hwtcl |
0 |
| core16_pf6vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf6vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf6vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf6vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf6vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf6vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf6vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf6vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf6vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf6vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf6vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf6vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf6vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf6vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf6vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf6vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf6vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf7vf_virtio_capability_present_hwtcl |
0 |
| core16_pf7vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf7vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf7vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf7vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf7vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf7vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf7vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf7vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf7vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf7vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf7vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf7vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf7vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf7vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf7vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf7vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf7vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_cii_range_0_k_cii_pf_en0_attr_user_hwtcl |
1 |
| core16_cii_range_0_k_cii_start_addr0_attr_user_hwtcl |
0 |
| core16_cii_range_0_k_cii_addr_size0_attr_user_hwtcl |
4095 |
| core16_cii_range_1_k_cii_pf_en1_attr_user_hwtcl |
0 |
| core16_cii_range_1_k_cii_start_addr1_attr_user_hwtcl |
0 |
| core16_cii_range_1_k_cii_addr_size1_attr_user_hwtcl |
0 |
| core16_cii_range_2_k_cii_pf_en2_attr_user_hwtcl |
0 |
| core16_cii_range_2_k_cii_start_addr2_attr_user_hwtcl |
0 |
| core16_cii_range_2_k_cii_addr_size2_attr_user_hwtcl |
0 |
| core16_cii_range_3_k_cii_pf_en3_attr_user_hwtcl |
0 |
| core16_cii_range_3_k_cii_start_addr3_attr_user_hwtcl |
0 |
| core16_cii_range_3_k_cii_addr_size3_attr_user_hwtcl |
0 |
| core16_cii_range_4_k_cii_pf_en4_attr_user_hwtcl |
0 |
| core16_cii_range_4_k_cii_start_addr4_attr_user_hwtcl |
0 |
| core16_cii_range_4_k_cii_addr_size4_attr_user_hwtcl |
0 |
| core16_cii_range_5_k_cii_pf_en5_attr_user_hwtcl |
0 |
| core16_cii_range_5_k_cii_start_addr5_attr_user_hwtcl |
0 |
| core16_cii_range_5_k_cii_addr_size5_attr_user_hwtcl |
0 |
| core16_cii_range_6_k_cii_pf_en6_attr_user_hwtcl |
0 |
| core16_cii_range_6_k_cii_start_addr6_attr_user_hwtcl |
0 |
| core16_cii_range_6_k_cii_addr_size6_attr_user_hwtcl |
0 |
| core16_ceb_enable_hwtcl |
0 |
| core16_pf_ceb_pointer_addr_user_hwtcl |
0 |
| core16_vf_ceb_pointer_addr_user_hwtcl |
0 |
| core16_pf0_bar0_type_user_hwtcl |
64-bit prefetchable memory |
| core16_pf0_bar0_address_width_user_hwtcl |
22 |
| core16_virtual_maxpayload_size_hwtcl |
512 |
| core16_cap_port_num_hwtcl |
1 |
| core16_cap_slot_clk_config_hwtcl |
0 |
| core16_pf0_gen2_ctrl_off_support_mod_ts_hwtcl |
1 |
| core16_virtual_pf0_msi_enable_user_hwtcl |
0 |
| core16_virtual_pf0_msix_enable_user_hwtcl |
1 |
| core16_pf0_pci_msix_table_size_hwtcl |
3 |
| core16_pf0_pci_msix_table_offset_hwtcl |
131072 |
| core16_pf0_pci_msix_bir_hwtcl |
0 |
| core16_pf0_pci_msix_pba_offset_hwtcl |
196608 |
| core16_pf0_pci_msix_pba_hwtcl |
0 |
| core16_exvf_msix_tablesize_pf0 |
0 |
| core16_exvf_msixtable_offset_pf0 |
0 |
| core16_exvf_msixtable_bir_pf0 |
0 |
| core16_exvf_msixpba_offset_pf0 |
0 |
| core16_exvf_msixpba_bir_pf0 |
0 |
| core16_exvf_msix_tablesize_pf1 |
0 |
| core16_exvf_msixtable_offset_pf1 |
0 |
| core16_exvf_msixtable_bir_pf1 |
0 |
| core16_exvf_msixpba_offset_pf1 |
0 |
| core16_exvf_msixpba_bir_pf1 |
0 |
| core16_exvf_msix_tablesize_pf2 |
0 |
| core16_exvf_msixtable_offset_pf2 |
0 |
| core16_exvf_msixtable_bir_pf2 |
0 |
| core16_exvf_msixpba_offset_pf2 |
0 |
| core16_exvf_msixpba_bir_pf2 |
0 |
| core16_exvf_msix_tablesize_pf3 |
0 |
| core16_exvf_msixtable_offset_pf3 |
0 |
| core16_exvf_msixtable_bir_pf3 |
0 |
| core16_exvf_msixpba_offset_pf3 |
0 |
| core16_exvf_msixpba_bir_pf3 |
0 |
| core16_exvf_msix_tablesize_pf4 |
0 |
| core16_exvf_msixtable_offset_pf4 |
0 |
| core16_exvf_msixtable_bir_pf4 |
0 |
| core16_exvf_msixpba_offset_pf4 |
0 |
| core16_exvf_msixpba_bir_pf4 |
0 |
| core16_exvf_msix_tablesize_pf5 |
0 |
| core16_exvf_msixtable_offset_pf5 |
0 |
| core16_exvf_msixtable_bir_pf5 |
0 |
| core16_exvf_msixpba_offset_pf5 |
0 |
| core16_exvf_msixpba_bir_pf5 |
0 |
| core16_exvf_msix_tablesize_pf6 |
0 |
| core16_exvf_msixtable_offset_pf6 |
0 |
| core16_exvf_msixtable_bir_pf6 |
0 |
| core16_exvf_msixpba_offset_pf6 |
0 |
| core16_exvf_msixpba_bir_pf6 |
0 |
| core16_exvf_msix_tablesize_pf7 |
0 |
| core16_exvf_msixtable_offset_pf7 |
0 |
| core16_exvf_msixtable_bir_pf7 |
0 |
| core16_exvf_msixpba_offset_pf7 |
0 |
| core16_exvf_msixpba_bir_pf7 |
0 |
| core16_virtual_pf0_prs_ext_cap_enable_hwtcl |
0 |
| core16_virtual_pf0_pasid_cap_enable_hwtcl |
0 |
| core16_virtual_dbi_ro_wr_disable_hwtcl |
0 |
| core16_virtual_sn_cap_enable_hwtcl |
0 |
| core16_sn_ser_num_reg_1_dw_hwtcl |
0 |
| core16_sn_ser_num_reg_2_dw_hwtcl |
0 |
| core16_user_pcie_cap_ep_l0s_accpt_latency_hwtcl |
0 |
| core16_user_pcie_cap_ep_l1_accpt_latency_hwtcl |
0 |
| core16_virtual_pf0_ltr_cap_enable_hwtcl |
0 |
| core16_pf0_pcie_slot_imp_hwtcl |
0 |
| core16_pf0_pcie_cap_slot_power_limit_scale_hwtcl |
0 |
| core16_pf0_pcie_cap_slot_power_limit_value_hwtcl |
0 |
| core16_pf0_pcie_cap_phy_slot_num_hwtcl |
0 |
| core16_virtual_ptm_hwtcl |
0 |
| core16_cfg_ptm_auto_update_period_hwtcl |
Disable |
| core16_virtual_pf0_ats_cap_enable_hwtcl |
0 |
| core16_virtual_pf0_tph_cap_enable_hwtcl |
0 |
| core16_virtual_pf0_acs_cap_enable_hwtcl |
0 |
| core16_pf0_pci_type0_vendor_id_user_hwtcl |
4794 |
| core16_pf0_pci_type0_device_id_hwtcl |
118 |
| core16_pf0_revision_id_user_hwtcl |
1 |
| core16_pf0_class_code_hwtcl |
1179648 |
| core16_pf0_subsys_vendor_id_hwtcl |
4794 |
| core16_pf0_subsys_dev_id_hwtcl |
46548 |
| core16_exvf_subsysid_pf0 |
0 |
| core16_exvf_subsysid_pf1 |
0 |
| core16_exvf_subsysid_pf2 |
0 |
| core16_exvf_subsysid_pf3 |
0 |
| core16_exvf_subsysid_pf4 |
0 |
| core16_exvf_subsysid_pf5 |
0 |
| core16_exvf_subsysid_pf6 |
0 |
| core16_exvf_subsysid_pf7 |
0 |
| core16_user_vsec_cap_enable_hwtcl |
0 |
| core16_cvp_user_id_hwtcl |
0 |
| core16_virtual_drop_vendor0_msg_hwtcl |
0 |
| core16_virtual_drop_vendor1_msg_hwtcl |
0 |
| core16_pf0_gen3_eq_pset_req_vec_user_hwtcl |
16 |
| core16_pf0_gen4_eq_pset_req_vec_user_hwtcl |
136 |
| core16_pf0_gen5_eq_pset_req_vec_user_hwtcl |
768 |
| core16_virtual_num_of_lanes_16_hwtcl |
16 |
| core16_pf0_int_pin_hwtcl |
NO INT |
| hssi_aib_ssm_silicon_rev |
14nm5 |
| hssi_aibnd_rx_0_aib_ber_margining_ctrl |
aib_ber_margining_setting0 |
| hssi_aibnd_rx_0_aib_datasel_gr0 |
aib_datasel0_setting0 |
| hssi_aibnd_rx_0_aib_datasel_gr1 |
aib_datasel1_setting1 |
| hssi_aibnd_rx_0_aib_datasel_gr2 |
aib_datasel2_setting1 |
| hssi_aibnd_rx_0_aib_dllstr_align_clkdiv |
aib_dllstr_align_clkdiv_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_dly_pst |
aib_dllstr_align_dly_pst_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_dy_ctl_static |
aib_dllstr_align_dy_ctl_static_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_dy_ctlsel |
aib_dllstr_align_dy_ctlsel_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_entest |
aib_dllstr_align_test_disable |
| hssi_aibnd_rx_0_aib_dllstr_align_halfcode |
aib_dllstr_align_halfcode_enable |
| hssi_aibnd_rx_0_aib_dllstr_align_selflock |
aib_dllstr_align_selflock_enable |
| hssi_aibnd_rx_0_aib_dllstr_align_st_core_dn_prgmnvrt |
aib_dllstr_align_st_core_dn_prgmnvrt_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_st_core_up_prgmnvrt |
aib_dllstr_align_st_core_up_prgmnvrt_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_st_core_updnen |
aib_dllstr_align_st_core_updnen_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_st_dftmuxsel |
aib_dllstr_align_st_dftmuxsel_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_st_en |
aib_dllstr_align_st_en_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_st_hps_ctrl_en |
aib_dllstr_align_hps_ctrl_en_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_st_lockreq_muxsel |
aib_dllstr_align_st_lockreq_muxsel_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_st_new_dll |
aib_dllstr_align_new_dll_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_st_rst |
aib_dllstr_align_st_rst_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_st_rst_prgmnvrt |
aib_dllstr_align_st_rst_prgmnvrt_setting0 |
| hssi_aibnd_rx_0_aib_dllstr_align_test_clk_pll_en_n |
aib_dllstr_align_test_clk_pll_en_n_disable |
| hssi_aibnd_rx_0_aib_inctrl_gr0 |
aib_inctrl0_setting0 |
| hssi_aibnd_rx_0_aib_inctrl_gr1 |
aib_inctrl1_setting0 |
| hssi_aibnd_rx_0_aib_inctrl_gr2 |
aib_inctrl2_setting0 |
| hssi_aibnd_rx_0_aib_inctrl_gr3 |
aib_inctrl3_setting0 |
| hssi_aibnd_rx_0_aib_outctrl_gr0 |
aib_outen0_setting0 |
| hssi_aibnd_rx_0_aib_outctrl_gr1 |
aib_outen1_setting0 |
| hssi_aibnd_rx_0_aib_outctrl_gr2 |
aib_outen2_setting0 |
| hssi_aibnd_rx_0_aib_outndrv_r12 |
aib_ndrv12_setting1 |
| hssi_aibnd_rx_0_aib_outndrv_r34 |
aib_ndrv34_setting1 |
| hssi_aibnd_rx_0_aib_outndrv_r56 |
aib_ndrv56_setting1 |
| hssi_aibnd_rx_0_aib_outndrv_r78 |
aib_ndrv78_setting1 |
| hssi_aibnd_rx_0_aib_outpdrv_r12 |
aib_pdrv12_setting1 |
| hssi_aibnd_rx_0_aib_outpdrv_r34 |
aib_pdrv34_setting1 |
| hssi_aibnd_rx_0_aib_outpdrv_r56 |
aib_pdrv56_setting1 |
| hssi_aibnd_rx_0_aib_outpdrv_r78 |
aib_pdrv78_setting1 |
| hssi_aibnd_rx_0_aib_red_shift_en |
aib_red_shift_disable |
| hssi_aibnd_rx_0_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_aibnd_rx_0_op_mode |
pwr_down |
| hssi_aibnd_rx_0_powerdown_mode |
true |
| hssi_aibnd_rx_0_powermode_ac |
rxdatapath_low_speed_pwr |
| hssi_aibnd_rx_0_powermode_dc |
rxdatapath_powerdown |
| hssi_aibnd_rx_0_powermode_freq_hz_aib_hssi_rx_transfer_clk |
0 |
| hssi_aibnd_rx_0_redundancy_en |
disable |
| hssi_aibnd_rx_0_sup_mode |
user_mode |
| hssi_aibnd_rx_0_silicon_rev |
14nm5 |
| hssi_aibnd_rx_13_aib_ber_margining_ctrl |
aib_ber_margining_setting0 |
| hssi_aibnd_rx_13_aib_datasel_gr0 |
aib_datasel0_setting0 |
| hssi_aibnd_rx_13_aib_datasel_gr1 |
aib_datasel1_setting1 |
| hssi_aibnd_rx_13_aib_datasel_gr2 |
aib_datasel2_setting1 |
| hssi_aibnd_rx_13_aib_dllstr_align_clkdiv |
aib_dllstr_align_clkdiv_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_dly_pst |
aib_dllstr_align_dly_pst_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_dy_ctl_static |
aib_dllstr_align_dy_ctl_static_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_dy_ctlsel |
aib_dllstr_align_dy_ctlsel_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_entest |
aib_dllstr_align_test_disable |
| hssi_aibnd_rx_13_aib_dllstr_align_halfcode |
aib_dllstr_align_halfcode_enable |
| hssi_aibnd_rx_13_aib_dllstr_align_selflock |
aib_dllstr_align_selflock_enable |
| hssi_aibnd_rx_13_aib_dllstr_align_st_core_dn_prgmnvrt |
aib_dllstr_align_st_core_dn_prgmnvrt_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_st_core_up_prgmnvrt |
aib_dllstr_align_st_core_up_prgmnvrt_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_st_core_updnen |
aib_dllstr_align_st_core_updnen_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_st_dftmuxsel |
aib_dllstr_align_st_dftmuxsel_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_st_en |
aib_dllstr_align_st_en_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_st_hps_ctrl_en |
aib_dllstr_align_hps_ctrl_en_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_st_lockreq_muxsel |
aib_dllstr_align_st_lockreq_muxsel_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_st_new_dll |
aib_dllstr_align_new_dll_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_st_rst |
aib_dllstr_align_st_rst_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_st_rst_prgmnvrt |
aib_dllstr_align_st_rst_prgmnvrt_setting0 |
| hssi_aibnd_rx_13_aib_dllstr_align_test_clk_pll_en_n |
aib_dllstr_align_test_clk_pll_en_n_disable |
| hssi_aibnd_rx_13_aib_inctrl_gr0 |
aib_inctrl0_setting0 |
| hssi_aibnd_rx_13_aib_inctrl_gr1 |
aib_inctrl1_setting0 |
| hssi_aibnd_rx_13_aib_inctrl_gr2 |
aib_inctrl2_setting0 |
| hssi_aibnd_rx_13_aib_inctrl_gr3 |
aib_inctrl3_setting0 |
| hssi_aibnd_rx_13_aib_outctrl_gr0 |
aib_outen0_setting0 |
| hssi_aibnd_rx_13_aib_outctrl_gr1 |
aib_outen1_setting0 |
| hssi_aibnd_rx_13_aib_outctrl_gr2 |
aib_outen2_setting0 |
| hssi_aibnd_rx_13_aib_outndrv_r12 |
aib_ndrv12_setting1 |
| hssi_aibnd_rx_13_aib_outndrv_r34 |
aib_ndrv34_setting1 |
| hssi_aibnd_rx_13_aib_outndrv_r56 |
aib_ndrv56_setting1 |
| hssi_aibnd_rx_13_aib_outndrv_r78 |
aib_ndrv78_setting1 |
| hssi_aibnd_rx_13_aib_outpdrv_r12 |
aib_pdrv12_setting1 |
| hssi_aibnd_rx_13_aib_outpdrv_r34 |
aib_pdrv34_setting1 |
| hssi_aibnd_rx_13_aib_outpdrv_r56 |
aib_pdrv56_setting1 |
| hssi_aibnd_rx_13_aib_outpdrv_r78 |
aib_pdrv78_setting1 |
| hssi_aibnd_rx_13_aib_red_shift_en |
aib_red_shift_disable |
| hssi_aibnd_rx_13_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_aibnd_rx_13_op_mode |
pwr_down |
| hssi_aibnd_rx_13_powerdown_mode |
true |
| hssi_aibnd_rx_13_powermode_ac |
rxdatapath_low_speed_pwr |
| hssi_aibnd_rx_13_powermode_dc |
rxdatapath_powerdown |
| hssi_aibnd_rx_13_powermode_freq_hz_aib_hssi_rx_transfer_clk |
0 |
| hssi_aibnd_rx_13_redundancy_en |
disable |
| hssi_aibnd_rx_13_sup_mode |
user_mode |
| hssi_aibnd_rx_13_silicon_rev |
14nm5 |
| hssi_aibnd_rx_15_aib_ber_margining_ctrl |
aib_ber_margining_setting0 |
| hssi_aibnd_rx_15_aib_datasel_gr0 |
aib_datasel0_setting0 |
| hssi_aibnd_rx_15_aib_datasel_gr1 |
aib_datasel1_setting1 |
| hssi_aibnd_rx_15_aib_datasel_gr2 |
aib_datasel2_setting1 |
| hssi_aibnd_rx_15_aib_dllstr_align_clkdiv |
aib_dllstr_align_clkdiv_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_dly_pst |
aib_dllstr_align_dly_pst_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_dy_ctl_static |
aib_dllstr_align_dy_ctl_static_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_dy_ctlsel |
aib_dllstr_align_dy_ctlsel_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_entest |
aib_dllstr_align_test_disable |
| hssi_aibnd_rx_15_aib_dllstr_align_halfcode |
aib_dllstr_align_halfcode_enable |
| hssi_aibnd_rx_15_aib_dllstr_align_selflock |
aib_dllstr_align_selflock_enable |
| hssi_aibnd_rx_15_aib_dllstr_align_st_core_dn_prgmnvrt |
aib_dllstr_align_st_core_dn_prgmnvrt_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_st_core_up_prgmnvrt |
aib_dllstr_align_st_core_up_prgmnvrt_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_st_core_updnen |
aib_dllstr_align_st_core_updnen_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_st_dftmuxsel |
aib_dllstr_align_st_dftmuxsel_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_st_en |
aib_dllstr_align_st_en_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_st_hps_ctrl_en |
aib_dllstr_align_hps_ctrl_en_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_st_lockreq_muxsel |
aib_dllstr_align_st_lockreq_muxsel_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_st_new_dll |
aib_dllstr_align_new_dll_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_st_rst |
aib_dllstr_align_st_rst_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_st_rst_prgmnvrt |
aib_dllstr_align_st_rst_prgmnvrt_setting0 |
| hssi_aibnd_rx_15_aib_dllstr_align_test_clk_pll_en_n |
aib_dllstr_align_test_clk_pll_en_n_disable |
| hssi_aibnd_rx_15_aib_inctrl_gr0 |
aib_inctrl0_setting0 |
| hssi_aibnd_rx_15_aib_inctrl_gr1 |
aib_inctrl1_setting0 |
| hssi_aibnd_rx_15_aib_inctrl_gr2 |
aib_inctrl2_setting0 |
| hssi_aibnd_rx_15_aib_inctrl_gr3 |
aib_inctrl3_setting0 |
| hssi_aibnd_rx_15_aib_outctrl_gr0 |
aib_outen0_setting0 |
| hssi_aibnd_rx_15_aib_outctrl_gr1 |
aib_outen1_setting0 |
| hssi_aibnd_rx_15_aib_outctrl_gr2 |
aib_outen2_setting0 |
| hssi_aibnd_rx_15_aib_outndrv_r12 |
aib_ndrv12_setting1 |
| hssi_aibnd_rx_15_aib_outndrv_r34 |
aib_ndrv34_setting1 |
| hssi_aibnd_rx_15_aib_outndrv_r56 |
aib_ndrv56_setting1 |
| hssi_aibnd_rx_15_aib_outndrv_r78 |
aib_ndrv78_setting1 |
| hssi_aibnd_rx_15_aib_outpdrv_r12 |
aib_pdrv12_setting1 |
| hssi_aibnd_rx_15_aib_outpdrv_r34 |
aib_pdrv34_setting1 |
| hssi_aibnd_rx_15_aib_outpdrv_r56 |
aib_pdrv56_setting1 |
| hssi_aibnd_rx_15_aib_outpdrv_r78 |
aib_pdrv78_setting1 |
| hssi_aibnd_rx_15_aib_red_shift_en |
aib_red_shift_disable |
| hssi_aibnd_rx_15_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_aibnd_rx_15_op_mode |
pwr_down |
| hssi_aibnd_rx_15_powerdown_mode |
true |
| hssi_aibnd_rx_15_powermode_ac |
rxdatapath_low_speed_pwr |
| hssi_aibnd_rx_15_powermode_dc |
rxdatapath_powerdown |
| hssi_aibnd_rx_15_powermode_freq_hz_aib_hssi_rx_transfer_clk |
0 |
| hssi_aibnd_rx_15_redundancy_en |
disable |
| hssi_aibnd_rx_15_sup_mode |
user_mode |
| hssi_aibnd_rx_15_silicon_rev |
14nm5 |
| hssi_aibnd_rx_23_aib_ber_margining_ctrl |
aib_ber_margining_setting0 |
| hssi_aibnd_rx_23_aib_datasel_gr0 |
aib_datasel0_setting0 |
| hssi_aibnd_rx_23_aib_datasel_gr1 |
aib_datasel1_setting1 |
| hssi_aibnd_rx_23_aib_datasel_gr2 |
aib_datasel2_setting1 |
| hssi_aibnd_rx_23_aib_dllstr_align_clkdiv |
aib_dllstr_align_clkdiv_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_dly_pst |
aib_dllstr_align_dly_pst_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_dy_ctl_static |
aib_dllstr_align_dy_ctl_static_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_dy_ctlsel |
aib_dllstr_align_dy_ctlsel_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_entest |
aib_dllstr_align_test_disable |
| hssi_aibnd_rx_23_aib_dllstr_align_halfcode |
aib_dllstr_align_halfcode_enable |
| hssi_aibnd_rx_23_aib_dllstr_align_selflock |
aib_dllstr_align_selflock_enable |
| hssi_aibnd_rx_23_aib_dllstr_align_st_core_dn_prgmnvrt |
aib_dllstr_align_st_core_dn_prgmnvrt_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_st_core_up_prgmnvrt |
aib_dllstr_align_st_core_up_prgmnvrt_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_st_core_updnen |
aib_dllstr_align_st_core_updnen_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_st_dftmuxsel |
aib_dllstr_align_st_dftmuxsel_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_st_en |
aib_dllstr_align_st_en_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_st_hps_ctrl_en |
aib_dllstr_align_hps_ctrl_en_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_st_lockreq_muxsel |
aib_dllstr_align_st_lockreq_muxsel_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_st_new_dll |
aib_dllstr_align_new_dll_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_st_rst |
aib_dllstr_align_st_rst_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_st_rst_prgmnvrt |
aib_dllstr_align_st_rst_prgmnvrt_setting0 |
| hssi_aibnd_rx_23_aib_dllstr_align_test_clk_pll_en_n |
aib_dllstr_align_test_clk_pll_en_n_disable |
| hssi_aibnd_rx_23_aib_inctrl_gr0 |
aib_inctrl0_setting0 |
| hssi_aibnd_rx_23_aib_inctrl_gr1 |
aib_inctrl1_setting0 |
| hssi_aibnd_rx_23_aib_inctrl_gr2 |
aib_inctrl2_setting0 |
| hssi_aibnd_rx_23_aib_inctrl_gr3 |
aib_inctrl3_setting0 |
| hssi_aibnd_rx_23_aib_outctrl_gr0 |
aib_outen0_setting0 |
| hssi_aibnd_rx_23_aib_outctrl_gr1 |
aib_outen1_setting0 |
| hssi_aibnd_rx_23_aib_outctrl_gr2 |
aib_outen2_setting0 |
| hssi_aibnd_rx_23_aib_outndrv_r12 |
aib_ndrv12_setting1 |
| hssi_aibnd_rx_23_aib_outndrv_r34 |
aib_ndrv34_setting1 |
| hssi_aibnd_rx_23_aib_outndrv_r56 |
aib_ndrv56_setting1 |
| hssi_aibnd_rx_23_aib_outndrv_r78 |
aib_ndrv78_setting1 |
| hssi_aibnd_rx_23_aib_outpdrv_r12 |
aib_pdrv12_setting1 |
| hssi_aibnd_rx_23_aib_outpdrv_r34 |
aib_pdrv34_setting1 |
| hssi_aibnd_rx_23_aib_outpdrv_r56 |
aib_pdrv56_setting1 |
| hssi_aibnd_rx_23_aib_outpdrv_r78 |
aib_pdrv78_setting1 |
| hssi_aibnd_rx_23_aib_red_shift_en |
aib_red_shift_disable |
| hssi_aibnd_rx_23_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_aibnd_rx_23_op_mode |
pwr_down |
| hssi_aibnd_rx_23_powerdown_mode |
true |
| hssi_aibnd_rx_23_powermode_ac |
rxdatapath_low_speed_pwr |
| hssi_aibnd_rx_23_powermode_dc |
rxdatapath_powerdown |
| hssi_aibnd_rx_23_powermode_freq_hz_aib_hssi_rx_transfer_clk |
0 |
| hssi_aibnd_rx_23_redundancy_en |
disable |
| hssi_aibnd_rx_23_sup_mode |
user_mode |
| hssi_aibnd_rx_23_silicon_rev |
14nm5 |
| hssi_aibnd_tx_0_aib_datasel_gr0 |
aib_datasel0_setting0 |
| hssi_aibnd_tx_0_aib_datasel_gr1 |
aib_datasel1_setting0 |
| hssi_aibnd_tx_0_aib_datasel_gr2 |
aib_datasel2_setting1 |
| hssi_aibnd_tx_0_aib_datasel_gr3 |
aib_datasel3_setting1 |
| hssi_aibnd_tx_0_aib_ddrctrl_gr0 |
aib_ddr0_setting1 |
| hssi_aibnd_tx_0_aib_hssi_tx_transfer_clk_hz |
0 |
| hssi_aibnd_tx_0_aib_iinasyncen |
aib_inasyncen_setting0 |
| hssi_aibnd_tx_0_aib_iinclken |
aib_inclken_setting0 |
| hssi_aibnd_tx_0_aib_outctrl_gr0 |
aib_outen0_setting0 |
| hssi_aibnd_tx_0_aib_outctrl_gr1 |
aib_outen1_setting0 |
| hssi_aibnd_tx_0_aib_outctrl_gr2 |
aib_outen2_setting0 |
| hssi_aibnd_tx_0_aib_outctrl_gr3 |
aib_outen3_setting0 |
| hssi_aibnd_tx_0_aib_outndrv_r34 |
aib_ndrv34_setting1 |
| hssi_aibnd_tx_0_aib_outndrv_r56 |
aib_ndrv56_setting1 |
| hssi_aibnd_tx_0_aib_outpdrv_r34 |
aib_pdrv34_setting1 |
| hssi_aibnd_tx_0_aib_outpdrv_r56 |
aib_pdrv56_setting1 |
| hssi_aibnd_tx_0_aib_red_dirclkn_shiften |
aib_red_dirclkn_shift_disable |
| hssi_aibnd_tx_0_aib_red_dirclkp_shiften |
aib_red_dirclkp_shift_disable |
| hssi_aibnd_tx_0_aib_red_drx_shiften |
aib_red_drx_shift_disable |
| hssi_aibnd_tx_0_aib_red_dtx_shiften |
aib_red_dtx_shift_disable |
| hssi_aibnd_tx_0_aib_red_pout_shiften |
aib_red_pout_shift_disable |
| hssi_aibnd_tx_0_aib_red_rx_shiften |
aib_red_rx_shift_disable |
| hssi_aibnd_tx_0_aib_red_tx_shiften |
aib_red_tx_shift_disable |
| hssi_aibnd_tx_0_aib_red_txferclkout_shiften |
aib_red_txferclkout_shift_disable |
| hssi_aibnd_tx_0_aib_red_txferclkoutn_shiften |
aib_red_txferclkoutn_shift_disable |
| hssi_aibnd_tx_0_aib_tx_clkdiv |
aib_tx_clkdiv_setting1 |
| hssi_aibnd_tx_0_aib_tx_dcc_byp |
aib_tx_dcc_byp_disable |
| hssi_aibnd_tx_0_aib_tx_dcc_byp_iocsr_unused |
aib_tx_dcc_byp_disable_iocsr_unused |
| hssi_aibnd_tx_0_aib_tx_dcc_cont_cal |
aib_tx_dcc_cal_cont |
| hssi_aibnd_tx_0_aib_tx_dcc_cont_cal_iocsr_unused |
aib_tx_dcc_cal_single_iocsr_unused |
| hssi_aibnd_tx_0_aib_tx_dcc_dft |
aib_tx_dcc_dft_disable |
| hssi_aibnd_tx_0_aib_tx_dcc_dft_sel |
aib_tx_dcc_dft_mode0 |
| hssi_aibnd_tx_0_aib_tx_dcc_dll_dft_sel |
aib_tx_dcc_dll_dft_sel_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_dll_entest |
aib_tx_dcc_dll_test_disable |
| hssi_aibnd_tx_0_aib_tx_dcc_dy_ctl_static |
aib_tx_dcc_dy_ctl_static_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_dy_ctlsel |
aib_tx_dcc_dy_ctlsel_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_en |
aib_tx_dcc_enable |
| hssi_aibnd_tx_0_aib_tx_dcc_en_iocsr_unused |
aib_tx_dcc_disable_iocsr_unused |
| hssi_aibnd_tx_0_aib_tx_dcc_manual_dn |
aib_tx_dcc_manual_dn0 |
| hssi_aibnd_tx_0_aib_tx_dcc_manual_up |
aib_tx_dcc_manual_up0 |
| hssi_aibnd_tx_0_aib_tx_dcc_rst_prgmnvrt |
aib_tx_dcc_st_rst_prgmnvrt_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_st_core_dn_prgmnvrt |
aib_tx_dcc_st_core_dn_prgmnvrt_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_st_core_up_prgmnvrt |
aib_tx_dcc_st_core_up_prgmnvrt_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_st_core_updnen |
aib_tx_dcc_st_core_updnen_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_st_dftmuxsel |
aib_tx_dcc_st_dftmuxsel_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_st_dly_pst |
aib_tx_dcc_st_dly_pst_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_st_en |
aib_tx_dcc_st_en_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_st_hps_ctrl_en |
aib_tx_dcc_hps_ctrl_en_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_st_lockreq_muxsel |
aib_tx_dcc_st_lockreq_muxsel_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_st_new_dll |
aib_tx_dcc_new_dll_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_st_rst |
aib_tx_dcc_st_rst_setting0 |
| hssi_aibnd_tx_0_aib_tx_dcc_test_clk_pll_en_n |
aib_tx_dcc_test_clk_pll_en_n_disable |
| hssi_aibnd_tx_0_aib_tx_halfcode |
aib_tx_halfcode_enable |
| hssi_aibnd_tx_0_aib_tx_selflock |
aib_tx_selflock_enable |
| hssi_aibnd_tx_0_dfd_dll_dcc_en |
disable_dfd |
| hssi_aibnd_tx_0_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_aibnd_tx_0_op_mode |
tx_dcc_enable |
| hssi_aibnd_tx_0_powerdown_mode |
true |
| hssi_aibnd_tx_0_powermode_ac |
txdatapath_low_speed_pwr |
| hssi_aibnd_tx_0_powermode_dc |
txdatapath_powerdown |
| hssi_aibnd_tx_0_powermode_freq_hz_aib_hssi_tx_transfer_clk |
0 |
| hssi_aibnd_tx_0_redundancy_en |
disable |
| hssi_aibnd_tx_0_sup_mode |
user_mode |
| hssi_aibnd_tx_0_silicon_rev |
14nm5 |
| hssi_aibnd_tx_13_aib_datasel_gr0 |
aib_datasel0_setting0 |
| hssi_aibnd_tx_13_aib_datasel_gr1 |
aib_datasel1_setting0 |
| hssi_aibnd_tx_13_aib_datasel_gr2 |
aib_datasel2_setting1 |
| hssi_aibnd_tx_13_aib_datasel_gr3 |
aib_datasel3_setting1 |
| hssi_aibnd_tx_13_aib_ddrctrl_gr0 |
aib_ddr0_setting1 |
| hssi_aibnd_tx_13_aib_hssi_tx_transfer_clk_hz |
0 |
| hssi_aibnd_tx_13_aib_iinasyncen |
aib_inasyncen_setting0 |
| hssi_aibnd_tx_13_aib_iinclken |
aib_inclken_setting0 |
| hssi_aibnd_tx_13_aib_outctrl_gr0 |
aib_outen0_setting0 |
| hssi_aibnd_tx_13_aib_outctrl_gr1 |
aib_outen1_setting0 |
| hssi_aibnd_tx_13_aib_outctrl_gr2 |
aib_outen2_setting0 |
| hssi_aibnd_tx_13_aib_outctrl_gr3 |
aib_outen3_setting0 |
| hssi_aibnd_tx_13_aib_outndrv_r34 |
aib_ndrv34_setting1 |
| hssi_aibnd_tx_13_aib_outndrv_r56 |
aib_ndrv56_setting1 |
| hssi_aibnd_tx_13_aib_outpdrv_r34 |
aib_pdrv34_setting1 |
| hssi_aibnd_tx_13_aib_outpdrv_r56 |
aib_pdrv56_setting1 |
| hssi_aibnd_tx_13_aib_red_dirclkn_shiften |
aib_red_dirclkn_shift_disable |
| hssi_aibnd_tx_13_aib_red_dirclkp_shiften |
aib_red_dirclkp_shift_disable |
| hssi_aibnd_tx_13_aib_red_drx_shiften |
aib_red_drx_shift_disable |
| hssi_aibnd_tx_13_aib_red_dtx_shiften |
aib_red_dtx_shift_disable |
| hssi_aibnd_tx_13_aib_red_pout_shiften |
aib_red_pout_shift_disable |
| hssi_aibnd_tx_13_aib_red_rx_shiften |
aib_red_rx_shift_disable |
| hssi_aibnd_tx_13_aib_red_tx_shiften |
aib_red_tx_shift_disable |
| hssi_aibnd_tx_13_aib_red_txferclkout_shiften |
aib_red_txferclkout_shift_disable |
| hssi_aibnd_tx_13_aib_red_txferclkoutn_shiften |
aib_red_txferclkoutn_shift_disable |
| hssi_aibnd_tx_13_aib_tx_clkdiv |
aib_tx_clkdiv_setting1 |
| hssi_aibnd_tx_13_aib_tx_dcc_byp |
aib_tx_dcc_byp_disable |
| hssi_aibnd_tx_13_aib_tx_dcc_byp_iocsr_unused |
aib_tx_dcc_byp_disable_iocsr_unused |
| hssi_aibnd_tx_13_aib_tx_dcc_cont_cal |
aib_tx_dcc_cal_cont |
| hssi_aibnd_tx_13_aib_tx_dcc_cont_cal_iocsr_unused |
aib_tx_dcc_cal_single_iocsr_unused |
| hssi_aibnd_tx_13_aib_tx_dcc_dft |
aib_tx_dcc_dft_disable |
| hssi_aibnd_tx_13_aib_tx_dcc_dft_sel |
aib_tx_dcc_dft_mode0 |
| hssi_aibnd_tx_13_aib_tx_dcc_dll_dft_sel |
aib_tx_dcc_dll_dft_sel_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_dll_entest |
aib_tx_dcc_dll_test_disable |
| hssi_aibnd_tx_13_aib_tx_dcc_dy_ctl_static |
aib_tx_dcc_dy_ctl_static_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_dy_ctlsel |
aib_tx_dcc_dy_ctlsel_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_en |
aib_tx_dcc_enable |
| hssi_aibnd_tx_13_aib_tx_dcc_en_iocsr_unused |
aib_tx_dcc_disable_iocsr_unused |
| hssi_aibnd_tx_13_aib_tx_dcc_manual_dn |
aib_tx_dcc_manual_dn0 |
| hssi_aibnd_tx_13_aib_tx_dcc_manual_up |
aib_tx_dcc_manual_up0 |
| hssi_aibnd_tx_13_aib_tx_dcc_rst_prgmnvrt |
aib_tx_dcc_st_rst_prgmnvrt_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_st_core_dn_prgmnvrt |
aib_tx_dcc_st_core_dn_prgmnvrt_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_st_core_up_prgmnvrt |
aib_tx_dcc_st_core_up_prgmnvrt_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_st_core_updnen |
aib_tx_dcc_st_core_updnen_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_st_dftmuxsel |
aib_tx_dcc_st_dftmuxsel_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_st_dly_pst |
aib_tx_dcc_st_dly_pst_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_st_en |
aib_tx_dcc_st_en_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_st_hps_ctrl_en |
aib_tx_dcc_hps_ctrl_en_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_st_lockreq_muxsel |
aib_tx_dcc_st_lockreq_muxsel_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_st_new_dll |
aib_tx_dcc_new_dll_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_st_rst |
aib_tx_dcc_st_rst_setting0 |
| hssi_aibnd_tx_13_aib_tx_dcc_test_clk_pll_en_n |
aib_tx_dcc_test_clk_pll_en_n_disable |
| hssi_aibnd_tx_13_aib_tx_halfcode |
aib_tx_halfcode_enable |
| hssi_aibnd_tx_13_aib_tx_selflock |
aib_tx_selflock_enable |
| hssi_aibnd_tx_13_dfd_dll_dcc_en |
disable_dfd |
| hssi_aibnd_tx_13_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_aibnd_tx_13_op_mode |
tx_dcc_enable |
| hssi_aibnd_tx_13_powerdown_mode |
true |
| hssi_aibnd_tx_13_powermode_ac |
txdatapath_low_speed_pwr |
| hssi_aibnd_tx_13_powermode_dc |
txdatapath_powerdown |
| hssi_aibnd_tx_13_powermode_freq_hz_aib_hssi_tx_transfer_clk |
0 |
| hssi_aibnd_tx_13_redundancy_en |
disable |
| hssi_aibnd_tx_13_sup_mode |
user_mode |
| hssi_aibnd_tx_13_silicon_rev |
14nm5 |
| hssi_aibnd_tx_15_aib_datasel_gr0 |
aib_datasel0_setting0 |
| hssi_aibnd_tx_15_aib_datasel_gr1 |
aib_datasel1_setting0 |
| hssi_aibnd_tx_15_aib_datasel_gr2 |
aib_datasel2_setting1 |
| hssi_aibnd_tx_15_aib_datasel_gr3 |
aib_datasel3_setting1 |
| hssi_aibnd_tx_15_aib_ddrctrl_gr0 |
aib_ddr0_setting1 |
| hssi_aibnd_tx_15_aib_hssi_tx_transfer_clk_hz |
0 |
| hssi_aibnd_tx_15_aib_iinasyncen |
aib_inasyncen_setting0 |
| hssi_aibnd_tx_15_aib_iinclken |
aib_inclken_setting0 |
| hssi_aibnd_tx_15_aib_outctrl_gr0 |
aib_outen0_setting0 |
| hssi_aibnd_tx_15_aib_outctrl_gr1 |
aib_outen1_setting0 |
| hssi_aibnd_tx_15_aib_outctrl_gr2 |
aib_outen2_setting0 |
| hssi_aibnd_tx_15_aib_outctrl_gr3 |
aib_outen3_setting0 |
| hssi_aibnd_tx_15_aib_outndrv_r34 |
aib_ndrv34_setting1 |
| hssi_aibnd_tx_15_aib_outndrv_r56 |
aib_ndrv56_setting1 |
| hssi_aibnd_tx_15_aib_outpdrv_r34 |
aib_pdrv34_setting1 |
| hssi_aibnd_tx_15_aib_outpdrv_r56 |
aib_pdrv56_setting1 |
| hssi_aibnd_tx_15_aib_red_dirclkn_shiften |
aib_red_dirclkn_shift_disable |
| hssi_aibnd_tx_15_aib_red_dirclkp_shiften |
aib_red_dirclkp_shift_disable |
| hssi_aibnd_tx_15_aib_red_drx_shiften |
aib_red_drx_shift_disable |
| hssi_aibnd_tx_15_aib_red_dtx_shiften |
aib_red_dtx_shift_disable |
| hssi_aibnd_tx_15_aib_red_pout_shiften |
aib_red_pout_shift_disable |
| hssi_aibnd_tx_15_aib_red_rx_shiften |
aib_red_rx_shift_disable |
| hssi_aibnd_tx_15_aib_red_tx_shiften |
aib_red_tx_shift_disable |
| hssi_aibnd_tx_15_aib_red_txferclkout_shiften |
aib_red_txferclkout_shift_disable |
| hssi_aibnd_tx_15_aib_red_txferclkoutn_shiften |
aib_red_txferclkoutn_shift_disable |
| hssi_aibnd_tx_15_aib_tx_clkdiv |
aib_tx_clkdiv_setting1 |
| hssi_aibnd_tx_15_aib_tx_dcc_byp |
aib_tx_dcc_byp_disable |
| hssi_aibnd_tx_15_aib_tx_dcc_byp_iocsr_unused |
aib_tx_dcc_byp_disable_iocsr_unused |
| hssi_aibnd_tx_15_aib_tx_dcc_cont_cal |
aib_tx_dcc_cal_cont |
| hssi_aibnd_tx_15_aib_tx_dcc_cont_cal_iocsr_unused |
aib_tx_dcc_cal_single_iocsr_unused |
| hssi_aibnd_tx_15_aib_tx_dcc_dft |
aib_tx_dcc_dft_disable |
| hssi_aibnd_tx_15_aib_tx_dcc_dft_sel |
aib_tx_dcc_dft_mode0 |
| hssi_aibnd_tx_15_aib_tx_dcc_dll_dft_sel |
aib_tx_dcc_dll_dft_sel_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_dll_entest |
aib_tx_dcc_dll_test_disable |
| hssi_aibnd_tx_15_aib_tx_dcc_dy_ctl_static |
aib_tx_dcc_dy_ctl_static_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_dy_ctlsel |
aib_tx_dcc_dy_ctlsel_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_en |
aib_tx_dcc_enable |
| hssi_aibnd_tx_15_aib_tx_dcc_en_iocsr_unused |
aib_tx_dcc_disable_iocsr_unused |
| hssi_aibnd_tx_15_aib_tx_dcc_manual_dn |
aib_tx_dcc_manual_dn0 |
| hssi_aibnd_tx_15_aib_tx_dcc_manual_up |
aib_tx_dcc_manual_up0 |
| hssi_aibnd_tx_15_aib_tx_dcc_rst_prgmnvrt |
aib_tx_dcc_st_rst_prgmnvrt_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_st_core_dn_prgmnvrt |
aib_tx_dcc_st_core_dn_prgmnvrt_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_st_core_up_prgmnvrt |
aib_tx_dcc_st_core_up_prgmnvrt_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_st_core_updnen |
aib_tx_dcc_st_core_updnen_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_st_dftmuxsel |
aib_tx_dcc_st_dftmuxsel_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_st_dly_pst |
aib_tx_dcc_st_dly_pst_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_st_en |
aib_tx_dcc_st_en_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_st_hps_ctrl_en |
aib_tx_dcc_hps_ctrl_en_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_st_lockreq_muxsel |
aib_tx_dcc_st_lockreq_muxsel_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_st_new_dll |
aib_tx_dcc_new_dll_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_st_rst |
aib_tx_dcc_st_rst_setting0 |
| hssi_aibnd_tx_15_aib_tx_dcc_test_clk_pll_en_n |
aib_tx_dcc_test_clk_pll_en_n_disable |
| hssi_aibnd_tx_15_aib_tx_halfcode |
aib_tx_halfcode_enable |
| hssi_aibnd_tx_15_aib_tx_selflock |
aib_tx_selflock_enable |
| hssi_aibnd_tx_15_dfd_dll_dcc_en |
disable_dfd |
| hssi_aibnd_tx_15_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_aibnd_tx_15_op_mode |
tx_dcc_enable |
| hssi_aibnd_tx_15_powerdown_mode |
true |
| hssi_aibnd_tx_15_powermode_ac |
txdatapath_low_speed_pwr |
| hssi_aibnd_tx_15_powermode_dc |
txdatapath_powerdown |
| hssi_aibnd_tx_15_powermode_freq_hz_aib_hssi_tx_transfer_clk |
0 |
| hssi_aibnd_tx_15_redundancy_en |
disable |
| hssi_aibnd_tx_15_sup_mode |
user_mode |
| hssi_aibnd_tx_15_silicon_rev |
14nm5 |
| hssi_aibnd_tx_23_aib_datasel_gr0 |
aib_datasel0_setting0 |
| hssi_aibnd_tx_23_aib_datasel_gr1 |
aib_datasel1_setting0 |
| hssi_aibnd_tx_23_aib_datasel_gr2 |
aib_datasel2_setting1 |
| hssi_aibnd_tx_23_aib_datasel_gr3 |
aib_datasel3_setting1 |
| hssi_aibnd_tx_23_aib_ddrctrl_gr0 |
aib_ddr0_setting1 |
| hssi_aibnd_tx_23_aib_hssi_tx_transfer_clk_hz |
0 |
| hssi_aibnd_tx_23_aib_iinasyncen |
aib_inasyncen_setting0 |
| hssi_aibnd_tx_23_aib_iinclken |
aib_inclken_setting0 |
| hssi_aibnd_tx_23_aib_outctrl_gr0 |
aib_outen0_setting0 |
| hssi_aibnd_tx_23_aib_outctrl_gr1 |
aib_outen1_setting0 |
| hssi_aibnd_tx_23_aib_outctrl_gr2 |
aib_outen2_setting0 |
| hssi_aibnd_tx_23_aib_outctrl_gr3 |
aib_outen3_setting0 |
| hssi_aibnd_tx_23_aib_outndrv_r34 |
aib_ndrv34_setting1 |
| hssi_aibnd_tx_23_aib_outndrv_r56 |
aib_ndrv56_setting1 |
| hssi_aibnd_tx_23_aib_outpdrv_r34 |
aib_pdrv34_setting1 |
| hssi_aibnd_tx_23_aib_outpdrv_r56 |
aib_pdrv56_setting1 |
| hssi_aibnd_tx_23_aib_red_dirclkn_shiften |
aib_red_dirclkn_shift_disable |
| hssi_aibnd_tx_23_aib_red_dirclkp_shiften |
aib_red_dirclkp_shift_disable |
| hssi_aibnd_tx_23_aib_red_drx_shiften |
aib_red_drx_shift_disable |
| hssi_aibnd_tx_23_aib_red_dtx_shiften |
aib_red_dtx_shift_disable |
| hssi_aibnd_tx_23_aib_red_pout_shiften |
aib_red_pout_shift_disable |
| hssi_aibnd_tx_23_aib_red_rx_shiften |
aib_red_rx_shift_disable |
| hssi_aibnd_tx_23_aib_red_tx_shiften |
aib_red_tx_shift_disable |
| hssi_aibnd_tx_23_aib_red_txferclkout_shiften |
aib_red_txferclkout_shift_disable |
| hssi_aibnd_tx_23_aib_red_txferclkoutn_shiften |
aib_red_txferclkoutn_shift_disable |
| hssi_aibnd_tx_23_aib_tx_clkdiv |
aib_tx_clkdiv_setting1 |
| hssi_aibnd_tx_23_aib_tx_dcc_byp |
aib_tx_dcc_byp_disable |
| hssi_aibnd_tx_23_aib_tx_dcc_byp_iocsr_unused |
aib_tx_dcc_byp_disable_iocsr_unused |
| hssi_aibnd_tx_23_aib_tx_dcc_cont_cal |
aib_tx_dcc_cal_cont |
| hssi_aibnd_tx_23_aib_tx_dcc_cont_cal_iocsr_unused |
aib_tx_dcc_cal_single_iocsr_unused |
| hssi_aibnd_tx_23_aib_tx_dcc_dft |
aib_tx_dcc_dft_disable |
| hssi_aibnd_tx_23_aib_tx_dcc_dft_sel |
aib_tx_dcc_dft_mode0 |
| hssi_aibnd_tx_23_aib_tx_dcc_dll_dft_sel |
aib_tx_dcc_dll_dft_sel_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_dll_entest |
aib_tx_dcc_dll_test_disable |
| hssi_aibnd_tx_23_aib_tx_dcc_dy_ctl_static |
aib_tx_dcc_dy_ctl_static_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_dy_ctlsel |
aib_tx_dcc_dy_ctlsel_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_en |
aib_tx_dcc_enable |
| hssi_aibnd_tx_23_aib_tx_dcc_en_iocsr_unused |
aib_tx_dcc_disable_iocsr_unused |
| hssi_aibnd_tx_23_aib_tx_dcc_manual_dn |
aib_tx_dcc_manual_dn0 |
| hssi_aibnd_tx_23_aib_tx_dcc_manual_up |
aib_tx_dcc_manual_up0 |
| hssi_aibnd_tx_23_aib_tx_dcc_rst_prgmnvrt |
aib_tx_dcc_st_rst_prgmnvrt_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_st_core_dn_prgmnvrt |
aib_tx_dcc_st_core_dn_prgmnvrt_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_st_core_up_prgmnvrt |
aib_tx_dcc_st_core_up_prgmnvrt_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_st_core_updnen |
aib_tx_dcc_st_core_updnen_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_st_dftmuxsel |
aib_tx_dcc_st_dftmuxsel_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_st_dly_pst |
aib_tx_dcc_st_dly_pst_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_st_en |
aib_tx_dcc_st_en_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_st_hps_ctrl_en |
aib_tx_dcc_hps_ctrl_en_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_st_lockreq_muxsel |
aib_tx_dcc_st_lockreq_muxsel_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_st_new_dll |
aib_tx_dcc_new_dll_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_st_rst |
aib_tx_dcc_st_rst_setting0 |
| hssi_aibnd_tx_23_aib_tx_dcc_test_clk_pll_en_n |
aib_tx_dcc_test_clk_pll_en_n_disable |
| hssi_aibnd_tx_23_aib_tx_halfcode |
aib_tx_halfcode_enable |
| hssi_aibnd_tx_23_aib_tx_selflock |
aib_tx_selflock_enable |
| hssi_aibnd_tx_23_dfd_dll_dcc_en |
disable_dfd |
| hssi_aibnd_tx_23_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_aibnd_tx_23_op_mode |
tx_dcc_enable |
| hssi_aibnd_tx_23_powerdown_mode |
true |
| hssi_aibnd_tx_23_powermode_ac |
txdatapath_low_speed_pwr |
| hssi_aibnd_tx_23_powermode_dc |
txdatapath_powerdown |
| hssi_aibnd_tx_23_powermode_freq_hz_aib_hssi_tx_transfer_clk |
0 |
| hssi_aibnd_tx_23_redundancy_en |
disable |
| hssi_aibnd_tx_23_sup_mode |
user_mode |
| hssi_aibnd_tx_23_silicon_rev |
14nm5 |
| hssi_avmm1_if_0_pcs_arbiter_ctrl |
avmm1_arbiter_uc_sel |
| hssi_avmm1_if_0_hssiadapt_avmm_clk_dcg_en |
disable |
| hssi_avmm1_if_0_hssiadapt_avmm_clk_scg_en |
disable |
| hssi_avmm1_if_0_pldadapt_avmm_clk_scg_en |
disable |
| hssi_avmm1_if_0_pcs_cal_done |
avmm1_cal_done_assert |
| hssi_avmm1_if_0_pcs_cal_reserved |
0 |
| hssi_avmm1_if_0_pcs_calibration_feature_en |
avmm1_pcs_calibration_dis |
| hssi_avmm1_if_0_pldadapt_gate_dis |
disable |
| hssi_avmm1_if_0_pcs_hip_cal_en |
disable |
| hssi_avmm1_if_0_hssiadapt_nfhssi_calibratio_feature_en |
disable |
| hssi_avmm1_if_0_pldadapt_nfhssi_calibratio_feature_en |
disable |
| hssi_avmm1_if_0_hssiadapt_osc_clk_scg_en |
disable |
| hssi_avmm1_if_0_pldadapt_osc_clk_scg_en |
disable |
| hssi_avmm1_if_0_hssiadapt_read_blocking_enable |
enable |
| hssi_avmm1_if_0_pldadapt_read_blocking_enable |
enable |
| hssi_avmm1_if_0_hssiadapt_uc_blocking_enable |
enable |
| hssi_avmm1_if_0_pldadapt_uc_blocking_enable |
enable |
| hssi_avmm1_if_0_hssiadapt_write_resp_en |
disable |
| hssi_avmm1_if_0_hssiadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm1_if_0_pldadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm1_if_0_hssiadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm1_if_0_pldadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm1_if_0_func_mode |
c3adpt_pmadir |
| hssi_avmm1_if_0_hssiadapt_sr_hip_mode |
disable_hip |
| hssi_avmm1_if_0_hssiadapt_hip_mode |
disable_hip |
| hssi_avmm1_if_0_pldadapt_hip_mode |
disable_hip |
| hssi_avmm1_if_0_hssiadapt_sr_powerdown_mode |
powerup |
| hssi_avmm1_if_0_hssiadapt_sr_sr_free_run_div_clk |
out_of_reset_sync |
| hssi_avmm1_if_0_hssiadapt_sr_sr_hip_en |
disable |
| hssi_avmm1_if_0_hssiadapt_sr_sr_osc_clk_div_sel |
non_div |
| hssi_avmm1_if_0_hssiadapt_sr_sr_osc_clk_scg_en |
disable |
| hssi_avmm1_if_0_hssiadapt_sr_sr_parity_en |
disable |
| hssi_avmm1_if_0_hssiadapt_sr_sr_reserved_in_en |
enable |
| hssi_avmm1_if_0_hssiadapt_sr_sr_reserved_out_en |
enable |
| hssi_avmm1_if_0_hssiadapt_sr_sup_mode |
user_mode |
| hssi_avmm1_if_0_topology |
disabled_block |
| hssi_avmm1_if_0_silicon_rev |
14nm5 |
| hssi_avmm1_if_0_calibration_type |
one_time |
| hssi_avmm1_if_13_pcs_arbiter_ctrl |
avmm1_arbiter_uc_sel |
| hssi_avmm1_if_13_hssiadapt_avmm_clk_dcg_en |
disable |
| hssi_avmm1_if_13_hssiadapt_avmm_clk_scg_en |
disable |
| hssi_avmm1_if_13_pldadapt_avmm_clk_scg_en |
disable |
| hssi_avmm1_if_13_pcs_cal_done |
avmm1_cal_done_assert |
| hssi_avmm1_if_13_pcs_cal_reserved |
0 |
| hssi_avmm1_if_13_pcs_calibration_feature_en |
avmm1_pcs_calibration_dis |
| hssi_avmm1_if_13_pldadapt_gate_dis |
disable |
| hssi_avmm1_if_13_pcs_hip_cal_en |
disable |
| hssi_avmm1_if_13_hssiadapt_nfhssi_calibratio_feature_en |
disable |
| hssi_avmm1_if_13_pldadapt_nfhssi_calibratio_feature_en |
disable |
| hssi_avmm1_if_13_hssiadapt_osc_clk_scg_en |
disable |
| hssi_avmm1_if_13_pldadapt_osc_clk_scg_en |
disable |
| hssi_avmm1_if_13_hssiadapt_read_blocking_enable |
enable |
| hssi_avmm1_if_13_pldadapt_read_blocking_enable |
enable |
| hssi_avmm1_if_13_hssiadapt_uc_blocking_enable |
enable |
| hssi_avmm1_if_13_pldadapt_uc_blocking_enable |
enable |
| hssi_avmm1_if_13_hssiadapt_write_resp_en |
disable |
| hssi_avmm1_if_13_hssiadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm1_if_13_pldadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm1_if_13_hssiadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm1_if_13_pldadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm1_if_13_func_mode |
c3adpt_pmadir |
| hssi_avmm1_if_13_hssiadapt_sr_hip_mode |
disable_hip |
| hssi_avmm1_if_13_hssiadapt_hip_mode |
disable_hip |
| hssi_avmm1_if_13_pldadapt_hip_mode |
disable_hip |
| hssi_avmm1_if_13_hssiadapt_sr_powerdown_mode |
powerup |
| hssi_avmm1_if_13_hssiadapt_sr_sr_free_run_div_clk |
out_of_reset_sync |
| hssi_avmm1_if_13_hssiadapt_sr_sr_hip_en |
disable |
| hssi_avmm1_if_13_hssiadapt_sr_sr_osc_clk_div_sel |
non_div |
| hssi_avmm1_if_13_hssiadapt_sr_sr_osc_clk_scg_en |
disable |
| hssi_avmm1_if_13_hssiadapt_sr_sr_parity_en |
disable |
| hssi_avmm1_if_13_hssiadapt_sr_sr_reserved_in_en |
enable |
| hssi_avmm1_if_13_hssiadapt_sr_sr_reserved_out_en |
enable |
| hssi_avmm1_if_13_hssiadapt_sr_sup_mode |
user_mode |
| hssi_avmm1_if_13_topology |
disabled_block |
| hssi_avmm1_if_13_silicon_rev |
14nm5 |
| hssi_avmm1_if_13_calibration_type |
one_time |
| hssi_avmm1_if_15_pcs_arbiter_ctrl |
avmm1_arbiter_uc_sel |
| hssi_avmm1_if_15_hssiadapt_avmm_clk_dcg_en |
disable |
| hssi_avmm1_if_15_hssiadapt_avmm_clk_scg_en |
disable |
| hssi_avmm1_if_15_pldadapt_avmm_clk_scg_en |
disable |
| hssi_avmm1_if_15_pcs_cal_done |
avmm1_cal_done_assert |
| hssi_avmm1_if_15_pcs_cal_reserved |
0 |
| hssi_avmm1_if_15_pcs_calibration_feature_en |
avmm1_pcs_calibration_dis |
| hssi_avmm1_if_15_pldadapt_gate_dis |
disable |
| hssi_avmm1_if_15_pcs_hip_cal_en |
disable |
| hssi_avmm1_if_15_hssiadapt_nfhssi_calibratio_feature_en |
disable |
| hssi_avmm1_if_15_pldadapt_nfhssi_calibratio_feature_en |
disable |
| hssi_avmm1_if_15_hssiadapt_osc_clk_scg_en |
disable |
| hssi_avmm1_if_15_pldadapt_osc_clk_scg_en |
disable |
| hssi_avmm1_if_15_hssiadapt_read_blocking_enable |
enable |
| hssi_avmm1_if_15_pldadapt_read_blocking_enable |
enable |
| hssi_avmm1_if_15_hssiadapt_uc_blocking_enable |
enable |
| hssi_avmm1_if_15_pldadapt_uc_blocking_enable |
enable |
| hssi_avmm1_if_15_hssiadapt_write_resp_en |
disable |
| hssi_avmm1_if_15_hssiadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm1_if_15_pldadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm1_if_15_hssiadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm1_if_15_pldadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm1_if_15_func_mode |
c3adpt_pmadir |
| hssi_avmm1_if_15_hssiadapt_sr_hip_mode |
disable_hip |
| hssi_avmm1_if_15_hssiadapt_hip_mode |
disable_hip |
| hssi_avmm1_if_15_pldadapt_hip_mode |
disable_hip |
| hssi_avmm1_if_15_hssiadapt_sr_powerdown_mode |
powerup |
| hssi_avmm1_if_15_hssiadapt_sr_sr_free_run_div_clk |
out_of_reset_sync |
| hssi_avmm1_if_15_hssiadapt_sr_sr_hip_en |
disable |
| hssi_avmm1_if_15_hssiadapt_sr_sr_osc_clk_div_sel |
non_div |
| hssi_avmm1_if_15_hssiadapt_sr_sr_osc_clk_scg_en |
disable |
| hssi_avmm1_if_15_hssiadapt_sr_sr_parity_en |
disable |
| hssi_avmm1_if_15_hssiadapt_sr_sr_reserved_in_en |
enable |
| hssi_avmm1_if_15_hssiadapt_sr_sr_reserved_out_en |
enable |
| hssi_avmm1_if_15_hssiadapt_sr_sup_mode |
user_mode |
| hssi_avmm1_if_15_topology |
disabled_block |
| hssi_avmm1_if_15_silicon_rev |
14nm5 |
| hssi_avmm1_if_15_calibration_type |
one_time |
| hssi_avmm1_if_23_pcs_arbiter_ctrl |
avmm1_arbiter_uc_sel |
| hssi_avmm1_if_23_hssiadapt_avmm_clk_dcg_en |
disable |
| hssi_avmm1_if_23_hssiadapt_avmm_clk_scg_en |
disable |
| hssi_avmm1_if_23_pldadapt_avmm_clk_scg_en |
disable |
| hssi_avmm1_if_23_pcs_cal_done |
avmm1_cal_done_assert |
| hssi_avmm1_if_23_pcs_cal_reserved |
0 |
| hssi_avmm1_if_23_pcs_calibration_feature_en |
avmm1_pcs_calibration_dis |
| hssi_avmm1_if_23_pldadapt_gate_dis |
disable |
| hssi_avmm1_if_23_pcs_hip_cal_en |
disable |
| hssi_avmm1_if_23_hssiadapt_nfhssi_calibratio_feature_en |
disable |
| hssi_avmm1_if_23_pldadapt_nfhssi_calibratio_feature_en |
disable |
| hssi_avmm1_if_23_hssiadapt_osc_clk_scg_en |
disable |
| hssi_avmm1_if_23_pldadapt_osc_clk_scg_en |
disable |
| hssi_avmm1_if_23_hssiadapt_read_blocking_enable |
enable |
| hssi_avmm1_if_23_pldadapt_read_blocking_enable |
enable |
| hssi_avmm1_if_23_hssiadapt_uc_blocking_enable |
enable |
| hssi_avmm1_if_23_pldadapt_uc_blocking_enable |
enable |
| hssi_avmm1_if_23_hssiadapt_write_resp_en |
disable |
| hssi_avmm1_if_23_hssiadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm1_if_23_pldadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm1_if_23_hssiadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm1_if_23_pldadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm1_if_23_func_mode |
c3adpt_pmadir |
| hssi_avmm1_if_23_hssiadapt_sr_hip_mode |
disable_hip |
| hssi_avmm1_if_23_hssiadapt_hip_mode |
disable_hip |
| hssi_avmm1_if_23_pldadapt_hip_mode |
disable_hip |
| hssi_avmm1_if_23_hssiadapt_sr_powerdown_mode |
powerup |
| hssi_avmm1_if_23_hssiadapt_sr_sr_free_run_div_clk |
out_of_reset_sync |
| hssi_avmm1_if_23_hssiadapt_sr_sr_hip_en |
disable |
| hssi_avmm1_if_23_hssiadapt_sr_sr_osc_clk_div_sel |
non_div |
| hssi_avmm1_if_23_hssiadapt_sr_sr_osc_clk_scg_en |
disable |
| hssi_avmm1_if_23_hssiadapt_sr_sr_parity_en |
disable |
| hssi_avmm1_if_23_hssiadapt_sr_sr_reserved_in_en |
enable |
| hssi_avmm1_if_23_hssiadapt_sr_sr_reserved_out_en |
enable |
| hssi_avmm1_if_23_hssiadapt_sr_sup_mode |
user_mode |
| hssi_avmm1_if_23_topology |
disabled_block |
| hssi_avmm1_if_23_silicon_rev |
14nm5 |
| hssi_avmm1_if_23_calibration_type |
one_time |
| hssi_avmm2_if_0_pcs_arbiter_ctrl |
avmm2_arbiter_uc_sel |
| hssi_avmm2_if_0_hssiadapt_avmm_clk_dcg_en |
disable |
| hssi_avmm2_if_0_hssiadapt_avmm_clk_scg_en |
disable |
| hssi_avmm2_if_0_pldadapt_avmm_clk_scg_en |
disable |
| hssi_avmm2_if_0_pcs_cal_done |
avmm2_cal_done_assert |
| hssi_avmm2_if_0_pcs_cal_reserved |
0 |
| hssi_avmm2_if_0_pcs_calibration_feature_en |
avmm2_pcs_calibration_dis |
| hssi_avmm2_if_0_pldadapt_gate_dis |
disable |
| hssi_avmm2_if_0_pcs_hip_cal_en |
disable |
| hssi_avmm2_if_0_hssiadapt_osc_clk_scg_en |
disable |
| hssi_avmm2_if_0_pldadapt_osc_clk_scg_en |
disable |
| hssi_avmm2_if_0_hssiadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm2_if_0_pldadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm2_if_0_hssiadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm2_if_0_pldadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm2_if_0_func_mode |
c3adpt_pmadir |
| hssi_avmm2_if_0_hssiadapt_hip_mode |
disable_hip |
| hssi_avmm2_if_0_pldadapt_hip_mode |
disable_hip |
| hssi_avmm2_if_0_topology |
disabled_block |
| hssi_avmm2_if_0_silicon_rev |
14nm5 |
| hssi_avmm2_if_0_calibration_type |
one_time |
| hssi_avmm2_if_13_pcs_arbiter_ctrl |
avmm2_arbiter_uc_sel |
| hssi_avmm2_if_13_hssiadapt_avmm_clk_dcg_en |
disable |
| hssi_avmm2_if_13_hssiadapt_avmm_clk_scg_en |
disable |
| hssi_avmm2_if_13_pldadapt_avmm_clk_scg_en |
disable |
| hssi_avmm2_if_13_pcs_cal_done |
avmm2_cal_done_assert |
| hssi_avmm2_if_13_pcs_cal_reserved |
0 |
| hssi_avmm2_if_13_pcs_calibration_feature_en |
avmm2_pcs_calibration_dis |
| hssi_avmm2_if_13_pldadapt_gate_dis |
disable |
| hssi_avmm2_if_13_pcs_hip_cal_en |
disable |
| hssi_avmm2_if_13_hssiadapt_osc_clk_scg_en |
disable |
| hssi_avmm2_if_13_pldadapt_osc_clk_scg_en |
disable |
| hssi_avmm2_if_13_hssiadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm2_if_13_pldadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm2_if_13_hssiadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm2_if_13_pldadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm2_if_13_func_mode |
c3adpt_pmadir |
| hssi_avmm2_if_13_hssiadapt_hip_mode |
disable_hip |
| hssi_avmm2_if_13_pldadapt_hip_mode |
disable_hip |
| hssi_avmm2_if_13_topology |
disabled_block |
| hssi_avmm2_if_13_silicon_rev |
14nm5 |
| hssi_avmm2_if_13_calibration_type |
one_time |
| hssi_avmm2_if_15_pcs_arbiter_ctrl |
avmm2_arbiter_uc_sel |
| hssi_avmm2_if_15_hssiadapt_avmm_clk_dcg_en |
disable |
| hssi_avmm2_if_15_hssiadapt_avmm_clk_scg_en |
disable |
| hssi_avmm2_if_15_pldadapt_avmm_clk_scg_en |
disable |
| hssi_avmm2_if_15_pcs_cal_done |
avmm2_cal_done_assert |
| hssi_avmm2_if_15_pcs_cal_reserved |
0 |
| hssi_avmm2_if_15_pcs_calibration_feature_en |
avmm2_pcs_calibration_dis |
| hssi_avmm2_if_15_pldadapt_gate_dis |
disable |
| hssi_avmm2_if_15_pcs_hip_cal_en |
disable |
| hssi_avmm2_if_15_hssiadapt_osc_clk_scg_en |
disable |
| hssi_avmm2_if_15_pldadapt_osc_clk_scg_en |
disable |
| hssi_avmm2_if_15_hssiadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm2_if_15_pldadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm2_if_15_hssiadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm2_if_15_pldadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm2_if_15_func_mode |
c3adpt_pmadir |
| hssi_avmm2_if_15_hssiadapt_hip_mode |
disable_hip |
| hssi_avmm2_if_15_pldadapt_hip_mode |
disable_hip |
| hssi_avmm2_if_15_topology |
disabled_block |
| hssi_avmm2_if_15_silicon_rev |
14nm5 |
| hssi_avmm2_if_15_calibration_type |
one_time |
| hssi_avmm2_if_23_pcs_arbiter_ctrl |
avmm2_arbiter_uc_sel |
| hssi_avmm2_if_23_hssiadapt_avmm_clk_dcg_en |
disable |
| hssi_avmm2_if_23_hssiadapt_avmm_clk_scg_en |
disable |
| hssi_avmm2_if_23_pldadapt_avmm_clk_scg_en |
disable |
| hssi_avmm2_if_23_pcs_cal_done |
avmm2_cal_done_assert |
| hssi_avmm2_if_23_pcs_cal_reserved |
0 |
| hssi_avmm2_if_23_pcs_calibration_feature_en |
avmm2_pcs_calibration_dis |
| hssi_avmm2_if_23_pldadapt_gate_dis |
disable |
| hssi_avmm2_if_23_pcs_hip_cal_en |
disable |
| hssi_avmm2_if_23_hssiadapt_osc_clk_scg_en |
disable |
| hssi_avmm2_if_23_pldadapt_osc_clk_scg_en |
disable |
| hssi_avmm2_if_23_hssiadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm2_if_23_pldadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
| hssi_avmm2_if_23_hssiadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm2_if_23_pldadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_avmm2_if_23_func_mode |
c3adpt_pmadir |
| hssi_avmm2_if_23_hssiadapt_hip_mode |
disable_hip |
| hssi_avmm2_if_23_pldadapt_hip_mode |
disable_hip |
| hssi_avmm2_if_23_topology |
disabled_block |
| hssi_avmm2_if_23_silicon_rev |
14nm5 |
| hssi_avmm2_if_23_calibration_type |
one_time |
| hssi_pldadapt_rx_0_aib_clk1_sel |
aib_clk1_rx_transfer_clk |
| hssi_pldadapt_rx_0_aib_clk2_sel |
aib_clk2_rx_transfer_clk |
| hssi_pldadapt_rx_0_hdpldadapt_aib_fabric_pld_pma_hclk_hz |
0 |
| hssi_pldadapt_rx_0_hdpldadapt_aib_fabric_rx_sr_clk_in_hz |
0 |
| hssi_pldadapt_rx_0_hdpldadapt_aib_fabric_rx_transfer_clk_hz |
0 |
| hssi_pldadapt_rx_0_asn_bypass_pma_pcie_sw_done |
disable |
| hssi_pldadapt_rx_0_asn_en |
disable |
| hssi_pldadapt_rx_0_asn_wait_for_dll_reset_cnt |
0 |
| hssi_pldadapt_rx_0_asn_wait_for_fifo_flush_cnt |
0 |
| hssi_pldadapt_rx_0_asn_wait_for_pma_pcie_sw_done_cnt |
0 |
| hssi_pldadapt_rx_0_bonding_dft_en |
dft_dis |
| hssi_pldadapt_rx_0_bonding_dft_val |
dft_0 |
| hssi_pldadapt_rx_0_chnl_bonding |
disable |
| hssi_pldadapt_rx_0_clock_del_measure_enable |
disable |
| hssi_pldadapt_rx_0_comp_cnt |
0 |
| hssi_pldadapt_rx_0_compin_sel |
compin_master |
| hssi_pldadapt_rx_0_hdpldadapt_csr_clk_hz |
0 |
| hssi_pldadapt_rx_0_ctrl_plane_bonding |
individual |
| hssi_pldadapt_rx_0_ds_bypass_pipeln |
ds_bypass_pipeln_dis |
| hssi_pldadapt_rx_0_ds_last_chnl |
ds_not_last_chnl |
| hssi_pldadapt_rx_0_ds_master |
ds_master_en |
| hssi_pldadapt_rx_0_duplex_mode |
disable |
| hssi_pldadapt_rx_0_dv_mode |
dv_mode_dis |
| hssi_pldadapt_rx_0_fifo_double_read |
fifo_double_read_dis |
| hssi_pldadapt_rx_0_fifo_mode |
phase_comp |
| hssi_pldadapt_rx_0_fifo_rd_clk_ins_sm_scg_en |
disable |
| hssi_pldadapt_rx_0_fifo_rd_clk_scg_en |
disable |
| hssi_pldadapt_rx_0_fifo_rd_clk_sel |
fifo_rd_clk_rx_transfer_clk |
| hssi_pldadapt_rx_0_fifo_stop_rd |
n_rd_empty |
| hssi_pldadapt_rx_0_fifo_stop_wr |
n_wr_full |
| hssi_pldadapt_rx_0_fifo_width |
fifo_single_width |
| hssi_pldadapt_rx_0_fifo_wr_clk_del_sm_scg_en |
disable |
| hssi_pldadapt_rx_0_fifo_wr_clk_scg_en |
disable |
| hssi_pldadapt_rx_0_fifo_wr_clk_sel |
fifo_wr_clk_rx_transfer_clk |
| hssi_pldadapt_rx_0_free_run_div_clk |
out_of_reset_sync |
| hssi_pldadapt_rx_0_fsr_pld_10g_rx_crc32_err_rst_val |
reset_to_zero_crc32 |
| hssi_pldadapt_rx_0_fsr_pld_8g_sigdet_out_rst_val |
reset_to_zero_sigdet |
| hssi_pldadapt_rx_0_fsr_pld_ltd_b_rst_val |
reset_to_zero_ltdb |
| hssi_pldadapt_rx_0_fsr_pld_ltr_rst_val |
reset_to_zero_ltr |
| hssi_pldadapt_rx_0_fsr_pld_rx_fifo_align_clr_rst_val |
reset_to_zero_alignclr |
| hssi_pldadapt_rx_0_gb_rx_idwidth |
idwidth_32 |
| hssi_pldadapt_rx_0_gb_rx_odwidth |
odwidth_66 |
| hssi_pldadapt_rx_0_hip_mode |
disable_hip |
| hssi_pldadapt_rx_0_hrdrst_align_bypass |
disable |
| hssi_pldadapt_rx_0_hrdrst_dll_lock_bypass |
disable |
| hssi_pldadapt_rx_0_hrdrst_rst_sm_dis |
enable_rx_rst_sm |
| hssi_pldadapt_rx_0_hrdrst_rx_osc_clk_scg_en |
disable |
| hssi_pldadapt_rx_0_hrdrst_user_ctl_en |
disable |
| hssi_pldadapt_rx_0_indv |
indv_en |
| hssi_pldadapt_rx_0_internal_clk1_sel1 |
pma_clks_or_txfiford_post_ct_mux_clk1_mux1 |
| hssi_pldadapt_rx_0_internal_clk1_sel2 |
pma_clks_clk1_mux2 |
| hssi_pldadapt_rx_0_internal_clk2_sel1 |
pma_clks_or_rxfifowr_post_ct_mux_clk2_mux1 |
| hssi_pldadapt_rx_0_internal_clk2_sel2 |
pma_clks_clk2_mux2 |
| hssi_pldadapt_rx_0_is_paired_with |
other |
| hssi_pldadapt_rx_0_loopback_mode |
disable |
| hssi_pldadapt_rx_0_low_latency_en |
disable |
| hssi_pldadapt_rx_0_lpbk_mode |
disable |
| hssi_pldadapt_rx_0_osc_clk_scg_en |
disable |
| hssi_pldadapt_rx_0_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_pldadapt_rx_0_pipe_enable |
disable |
| hssi_pldadapt_rx_0_pipe_mode |
disable_pipe |
| hssi_pldadapt_rx_0_hdpldadapt_pld_avmm1_clk_rowclk_hz |
0 |
| hssi_pldadapt_rx_0_hdpldadapt_pld_avmm2_clk_rowclk_hz |
0 |
| hssi_pldadapt_rx_0_pld_clk1_delay_en |
disable |
| hssi_pldadapt_rx_0_pld_clk1_delay_sel |
delay_path0 |
| hssi_pldadapt_rx_0_pld_clk1_inv_en |
disable |
| hssi_pldadapt_rx_0_pld_clk1_sel |
pld_clk1_rowclk |
| hssi_pldadapt_rx_0_hdpldadapt_pld_rx_clk1_dcm_hz |
0 |
| hssi_pldadapt_rx_0_hdpldadapt_pld_rx_clk1_rowclk_hz |
0 |
| hssi_pldadapt_rx_0_hdpldadapt_pld_sclk1_rowclk_hz |
0 |
| hssi_pldadapt_rx_0_hdpldadapt_pld_sclk2_rowclk_hz |
0 |
| hssi_pldadapt_rx_0_pma_hclk_scg_en |
disable |
| hssi_pldadapt_rx_0_powerdown_mode |
powerdown |
| hssi_pldadapt_rx_0_powermode_dc |
powerdown |
| hssi_pldadapt_rx_0_powermode_freq_hz_aib_fabric_rx_sr_clk_in |
0 |
| hssi_pldadapt_rx_0_powermode_freq_hz_pld_rx_clk1_dcm |
0 |
| hssi_pldadapt_rx_0_rx_datapath_tb_sel |
cp_bond |
| hssi_pldadapt_rx_0_rx_fastbond_rden |
rden_ds_del_us_del |
| hssi_pldadapt_rx_0_rx_fastbond_wren |
wren_ds_del_us_del |
| hssi_pldadapt_rx_0_rx_fifo_power_mode |
full_width_full_depth |
| hssi_pldadapt_rx_0_rx_fifo_read_latency_adjust |
disable |
| hssi_pldadapt_rx_0_rx_fifo_write_ctrl |
blklock_stops |
| hssi_pldadapt_rx_0_rx_fifo_write_latency_adjust |
disable |
| hssi_pldadapt_rx_0_rx_osc_clock_setting |
osc_clk_div_by1 |
| hssi_pldadapt_rx_0_rx_pld_8g_eidleinfersel_polling_bypass |
disable |
| hssi_pldadapt_rx_0_rx_pld_pma_eye_monitor_polling_bypass |
disable |
| hssi_pldadapt_rx_0_rx_pld_pma_pcie_switch_polling_bypass |
disable |
| hssi_pldadapt_rx_0_rx_pld_pma_reser_out_polling_bypass |
disable |
| hssi_pldadapt_rx_0_rx_prbs_flags_sr_enable |
disable |
| hssi_pldadapt_rx_0_rx_true_b2b |
b2b |
| hssi_pldadapt_rx_0_rx_usertest_sel |
enable |
| hssi_pldadapt_rx_0_rxfifo_empty |
empty_sw |
| hssi_pldadapt_rx_0_rxfifo_full |
full_pc_sw |
| hssi_pldadapt_rx_0_rxfifo_mode |
rxphase_comp |
| hssi_pldadapt_rx_0_rxfifo_pempty |
2 |
| hssi_pldadapt_rx_0_rxfifo_pfull |
48 |
| hssi_pldadapt_rx_0_rxfiford_post_ct_sel |
rxfiford_sclk_post_ct |
| hssi_pldadapt_rx_0_rxfifowr_post_ct_sel |
rxfifowr_sclk_post_ct |
| hssi_pldadapt_rx_0_sclk_sel |
sclk1_rowclk |
| hssi_pldadapt_rx_0_hdpldadapt_speed_grade |
dash_1 |
| hssi_pldadapt_rx_0_hdpldadapt_sr_sr_testbus_sel |
ssr_testbus |
| hssi_pldadapt_rx_0_stretch_num_stages |
zero_stage |
| hssi_pldadapt_rx_0_sup_mode |
user_mode |
| hssi_pldadapt_rx_0_txfiford_post_ct_sel |
txfiford_sclk_post_ct |
| hssi_pldadapt_rx_0_txfifowr_post_ct_sel |
txfifowr_sclk_post_ct |
| hssi_pldadapt_rx_0_us_bypass_pipeln |
us_bypass_pipeln_dis |
| hssi_pldadapt_rx_0_us_last_chnl |
us_not_last_chnl |
| hssi_pldadapt_rx_0_us_master |
us_master_en |
| hssi_pldadapt_rx_0_word_align |
wa_en |
| hssi_pldadapt_rx_0_word_align_enable |
disable |
| hssi_pldadapt_rx_0_silicon_rev |
14nm5 |
| hssi_pldadapt_rx_0_reconfig_settings |
{} |
| hssi_pldadapt_rx_13_aib_clk1_sel |
aib_clk1_rx_transfer_clk |
| hssi_pldadapt_rx_13_aib_clk2_sel |
aib_clk2_rx_transfer_clk |
| hssi_pldadapt_rx_13_hdpldadapt_aib_fabric_pld_pma_hclk_hz |
0 |
| hssi_pldadapt_rx_13_hdpldadapt_aib_fabric_rx_sr_clk_in_hz |
0 |
| hssi_pldadapt_rx_13_hdpldadapt_aib_fabric_rx_transfer_clk_hz |
0 |
| hssi_pldadapt_rx_13_asn_bypass_pma_pcie_sw_done |
disable |
| hssi_pldadapt_rx_13_asn_en |
disable |
| hssi_pldadapt_rx_13_asn_wait_for_dll_reset_cnt |
0 |
| hssi_pldadapt_rx_13_asn_wait_for_fifo_flush_cnt |
0 |
| hssi_pldadapt_rx_13_asn_wait_for_pma_pcie_sw_done_cnt |
0 |
| hssi_pldadapt_rx_13_bonding_dft_en |
dft_dis |
| hssi_pldadapt_rx_13_bonding_dft_val |
dft_0 |
| hssi_pldadapt_rx_13_chnl_bonding |
disable |
| hssi_pldadapt_rx_13_clock_del_measure_enable |
disable |
| hssi_pldadapt_rx_13_comp_cnt |
0 |
| hssi_pldadapt_rx_13_compin_sel |
compin_master |
| hssi_pldadapt_rx_13_hdpldadapt_csr_clk_hz |
0 |
| hssi_pldadapt_rx_13_ctrl_plane_bonding |
individual |
| hssi_pldadapt_rx_13_ds_bypass_pipeln |
ds_bypass_pipeln_dis |
| hssi_pldadapt_rx_13_ds_last_chnl |
ds_not_last_chnl |
| hssi_pldadapt_rx_13_ds_master |
ds_master_en |
| hssi_pldadapt_rx_13_duplex_mode |
disable |
| hssi_pldadapt_rx_13_dv_mode |
dv_mode_dis |
| hssi_pldadapt_rx_13_fifo_double_read |
fifo_double_read_dis |
| hssi_pldadapt_rx_13_fifo_mode |
phase_comp |
| hssi_pldadapt_rx_13_fifo_rd_clk_ins_sm_scg_en |
disable |
| hssi_pldadapt_rx_13_fifo_rd_clk_scg_en |
disable |
| hssi_pldadapt_rx_13_fifo_rd_clk_sel |
fifo_rd_clk_rx_transfer_clk |
| hssi_pldadapt_rx_13_fifo_stop_rd |
n_rd_empty |
| hssi_pldadapt_rx_13_fifo_stop_wr |
n_wr_full |
| hssi_pldadapt_rx_13_fifo_width |
fifo_single_width |
| hssi_pldadapt_rx_13_fifo_wr_clk_del_sm_scg_en |
disable |
| hssi_pldadapt_rx_13_fifo_wr_clk_scg_en |
disable |
| hssi_pldadapt_rx_13_fifo_wr_clk_sel |
fifo_wr_clk_rx_transfer_clk |
| hssi_pldadapt_rx_13_free_run_div_clk |
out_of_reset_sync |
| hssi_pldadapt_rx_13_fsr_pld_10g_rx_crc32_err_rst_val |
reset_to_zero_crc32 |
| hssi_pldadapt_rx_13_fsr_pld_8g_sigdet_out_rst_val |
reset_to_zero_sigdet |
| hssi_pldadapt_rx_13_fsr_pld_ltd_b_rst_val |
reset_to_zero_ltdb |
| hssi_pldadapt_rx_13_fsr_pld_ltr_rst_val |
reset_to_zero_ltr |
| hssi_pldadapt_rx_13_fsr_pld_rx_fifo_align_clr_rst_val |
reset_to_zero_alignclr |
| hssi_pldadapt_rx_13_gb_rx_idwidth |
idwidth_32 |
| hssi_pldadapt_rx_13_gb_rx_odwidth |
odwidth_66 |
| hssi_pldadapt_rx_13_hip_mode |
disable_hip |
| hssi_pldadapt_rx_13_hrdrst_align_bypass |
disable |
| hssi_pldadapt_rx_13_hrdrst_dll_lock_bypass |
disable |
| hssi_pldadapt_rx_13_hrdrst_rst_sm_dis |
enable_rx_rst_sm |
| hssi_pldadapt_rx_13_hrdrst_rx_osc_clk_scg_en |
disable |
| hssi_pldadapt_rx_13_hrdrst_user_ctl_en |
disable |
| hssi_pldadapt_rx_13_indv |
indv_en |
| hssi_pldadapt_rx_13_internal_clk1_sel1 |
pma_clks_or_txfiford_post_ct_mux_clk1_mux1 |
| hssi_pldadapt_rx_13_internal_clk1_sel2 |
pma_clks_clk1_mux2 |
| hssi_pldadapt_rx_13_internal_clk2_sel1 |
pma_clks_or_rxfifowr_post_ct_mux_clk2_mux1 |
| hssi_pldadapt_rx_13_internal_clk2_sel2 |
pma_clks_clk2_mux2 |
| hssi_pldadapt_rx_13_is_paired_with |
other |
| hssi_pldadapt_rx_13_loopback_mode |
disable |
| hssi_pldadapt_rx_13_low_latency_en |
disable |
| hssi_pldadapt_rx_13_lpbk_mode |
disable |
| hssi_pldadapt_rx_13_osc_clk_scg_en |
disable |
| hssi_pldadapt_rx_13_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_pldadapt_rx_13_pipe_enable |
disable |
| hssi_pldadapt_rx_13_pipe_mode |
disable_pipe |
| hssi_pldadapt_rx_13_hdpldadapt_pld_avmm1_clk_rowclk_hz |
0 |
| hssi_pldadapt_rx_13_hdpldadapt_pld_avmm2_clk_rowclk_hz |
0 |
| hssi_pldadapt_rx_13_pld_clk1_delay_en |
disable |
| hssi_pldadapt_rx_13_pld_clk1_delay_sel |
delay_path0 |
| hssi_pldadapt_rx_13_pld_clk1_inv_en |
disable |
| hssi_pldadapt_rx_13_pld_clk1_sel |
pld_clk1_rowclk |
| hssi_pldadapt_rx_13_hdpldadapt_pld_rx_clk1_dcm_hz |
0 |
| hssi_pldadapt_rx_13_hdpldadapt_pld_rx_clk1_rowclk_hz |
0 |
| hssi_pldadapt_rx_13_hdpldadapt_pld_sclk1_rowclk_hz |
0 |
| hssi_pldadapt_rx_13_hdpldadapt_pld_sclk2_rowclk_hz |
0 |
| hssi_pldadapt_rx_13_pma_hclk_scg_en |
disable |
| hssi_pldadapt_rx_13_powerdown_mode |
powerdown |
| hssi_pldadapt_rx_13_powermode_dc |
powerdown |
| hssi_pldadapt_rx_13_powermode_freq_hz_aib_fabric_rx_sr_clk_in |
0 |
| hssi_pldadapt_rx_13_powermode_freq_hz_pld_rx_clk1_dcm |
0 |
| hssi_pldadapt_rx_13_rx_datapath_tb_sel |
cp_bond |
| hssi_pldadapt_rx_13_rx_fastbond_rden |
rden_ds_del_us_del |
| hssi_pldadapt_rx_13_rx_fastbond_wren |
wren_ds_del_us_del |
| hssi_pldadapt_rx_13_rx_fifo_power_mode |
full_width_full_depth |
| hssi_pldadapt_rx_13_rx_fifo_read_latency_adjust |
disable |
| hssi_pldadapt_rx_13_rx_fifo_write_ctrl |
blklock_stops |
| hssi_pldadapt_rx_13_rx_fifo_write_latency_adjust |
disable |
| hssi_pldadapt_rx_13_rx_osc_clock_setting |
osc_clk_div_by1 |
| hssi_pldadapt_rx_13_rx_pld_8g_eidleinfersel_polling_bypass |
disable |
| hssi_pldadapt_rx_13_rx_pld_pma_eye_monitor_polling_bypass |
disable |
| hssi_pldadapt_rx_13_rx_pld_pma_pcie_switch_polling_bypass |
disable |
| hssi_pldadapt_rx_13_rx_pld_pma_reser_out_polling_bypass |
disable |
| hssi_pldadapt_rx_13_rx_prbs_flags_sr_enable |
disable |
| hssi_pldadapt_rx_13_rx_true_b2b |
b2b |
| hssi_pldadapt_rx_13_rx_usertest_sel |
enable |
| hssi_pldadapt_rx_13_rxfifo_empty |
empty_sw |
| hssi_pldadapt_rx_13_rxfifo_full |
full_pc_sw |
| hssi_pldadapt_rx_13_rxfifo_mode |
rxphase_comp |
| hssi_pldadapt_rx_13_rxfifo_pempty |
2 |
| hssi_pldadapt_rx_13_rxfifo_pfull |
48 |
| hssi_pldadapt_rx_13_rxfiford_post_ct_sel |
rxfiford_sclk_post_ct |
| hssi_pldadapt_rx_13_rxfifowr_post_ct_sel |
rxfifowr_sclk_post_ct |
| hssi_pldadapt_rx_13_sclk_sel |
sclk1_rowclk |
| hssi_pldadapt_rx_13_hdpldadapt_speed_grade |
dash_1 |
| hssi_pldadapt_rx_13_hdpldadapt_sr_sr_testbus_sel |
ssr_testbus |
| hssi_pldadapt_rx_13_stretch_num_stages |
zero_stage |
| hssi_pldadapt_rx_13_sup_mode |
user_mode |
| hssi_pldadapt_rx_13_txfiford_post_ct_sel |
txfiford_sclk_post_ct |
| hssi_pldadapt_rx_13_txfifowr_post_ct_sel |
txfifowr_sclk_post_ct |
| hssi_pldadapt_rx_13_us_bypass_pipeln |
us_bypass_pipeln_dis |
| hssi_pldadapt_rx_13_us_last_chnl |
us_not_last_chnl |
| hssi_pldadapt_rx_13_us_master |
us_master_en |
| hssi_pldadapt_rx_13_word_align |
wa_en |
| hssi_pldadapt_rx_13_word_align_enable |
disable |
| hssi_pldadapt_rx_13_silicon_rev |
14nm5 |
| hssi_pldadapt_rx_13_reconfig_settings |
{} |
| hssi_pldadapt_rx_15_aib_clk1_sel |
aib_clk1_rx_transfer_clk |
| hssi_pldadapt_rx_15_aib_clk2_sel |
aib_clk2_rx_transfer_clk |
| hssi_pldadapt_rx_15_hdpldadapt_aib_fabric_pld_pma_hclk_hz |
0 |
| hssi_pldadapt_rx_15_hdpldadapt_aib_fabric_rx_sr_clk_in_hz |
0 |
| hssi_pldadapt_rx_15_hdpldadapt_aib_fabric_rx_transfer_clk_hz |
0 |
| hssi_pldadapt_rx_15_asn_bypass_pma_pcie_sw_done |
disable |
| hssi_pldadapt_rx_15_asn_en |
disable |
| hssi_pldadapt_rx_15_asn_wait_for_dll_reset_cnt |
0 |
| hssi_pldadapt_rx_15_asn_wait_for_fifo_flush_cnt |
0 |
| hssi_pldadapt_rx_15_asn_wait_for_pma_pcie_sw_done_cnt |
0 |
| hssi_pldadapt_rx_15_bonding_dft_en |
dft_dis |
| hssi_pldadapt_rx_15_bonding_dft_val |
dft_0 |
| hssi_pldadapt_rx_15_chnl_bonding |
disable |
| hssi_pldadapt_rx_15_clock_del_measure_enable |
disable |
| hssi_pldadapt_rx_15_comp_cnt |
0 |
| hssi_pldadapt_rx_15_compin_sel |
compin_master |
| hssi_pldadapt_rx_15_hdpldadapt_csr_clk_hz |
0 |
| hssi_pldadapt_rx_15_ctrl_plane_bonding |
individual |
| hssi_pldadapt_rx_15_ds_bypass_pipeln |
ds_bypass_pipeln_dis |
| hssi_pldadapt_rx_15_ds_last_chnl |
ds_not_last_chnl |
| hssi_pldadapt_rx_15_ds_master |
ds_master_en |
| hssi_pldadapt_rx_15_duplex_mode |
disable |
| hssi_pldadapt_rx_15_dv_mode |
dv_mode_dis |
| hssi_pldadapt_rx_15_fifo_double_read |
fifo_double_read_dis |
| hssi_pldadapt_rx_15_fifo_mode |
phase_comp |
| hssi_pldadapt_rx_15_fifo_rd_clk_ins_sm_scg_en |
disable |
| hssi_pldadapt_rx_15_fifo_rd_clk_scg_en |
disable |
| hssi_pldadapt_rx_15_fifo_rd_clk_sel |
fifo_rd_clk_rx_transfer_clk |
| hssi_pldadapt_rx_15_fifo_stop_rd |
n_rd_empty |
| hssi_pldadapt_rx_15_fifo_stop_wr |
n_wr_full |
| hssi_pldadapt_rx_15_fifo_width |
fifo_single_width |
| hssi_pldadapt_rx_15_fifo_wr_clk_del_sm_scg_en |
disable |
| hssi_pldadapt_rx_15_fifo_wr_clk_scg_en |
disable |
| hssi_pldadapt_rx_15_fifo_wr_clk_sel |
fifo_wr_clk_rx_transfer_clk |
| hssi_pldadapt_rx_15_free_run_div_clk |
out_of_reset_sync |
| hssi_pldadapt_rx_15_fsr_pld_10g_rx_crc32_err_rst_val |
reset_to_zero_crc32 |
| hssi_pldadapt_rx_15_fsr_pld_8g_sigdet_out_rst_val |
reset_to_zero_sigdet |
| hssi_pldadapt_rx_15_fsr_pld_ltd_b_rst_val |
reset_to_zero_ltdb |
| hssi_pldadapt_rx_15_fsr_pld_ltr_rst_val |
reset_to_zero_ltr |
| hssi_pldadapt_rx_15_fsr_pld_rx_fifo_align_clr_rst_val |
reset_to_zero_alignclr |
| hssi_pldadapt_rx_15_gb_rx_idwidth |
idwidth_32 |
| hssi_pldadapt_rx_15_gb_rx_odwidth |
odwidth_66 |
| hssi_pldadapt_rx_15_hip_mode |
disable_hip |
| hssi_pldadapt_rx_15_hrdrst_align_bypass |
disable |
| hssi_pldadapt_rx_15_hrdrst_dll_lock_bypass |
disable |
| hssi_pldadapt_rx_15_hrdrst_rst_sm_dis |
enable_rx_rst_sm |
| hssi_pldadapt_rx_15_hrdrst_rx_osc_clk_scg_en |
disable |
| hssi_pldadapt_rx_15_hrdrst_user_ctl_en |
disable |
| hssi_pldadapt_rx_15_indv |
indv_en |
| hssi_pldadapt_rx_15_internal_clk1_sel1 |
pma_clks_or_txfiford_post_ct_mux_clk1_mux1 |
| hssi_pldadapt_rx_15_internal_clk1_sel2 |
pma_clks_clk1_mux2 |
| hssi_pldadapt_rx_15_internal_clk2_sel1 |
pma_clks_or_rxfifowr_post_ct_mux_clk2_mux1 |
| hssi_pldadapt_rx_15_internal_clk2_sel2 |
pma_clks_clk2_mux2 |
| hssi_pldadapt_rx_15_is_paired_with |
other |
| hssi_pldadapt_rx_15_loopback_mode |
disable |
| hssi_pldadapt_rx_15_low_latency_en |
disable |
| hssi_pldadapt_rx_15_lpbk_mode |
disable |
| hssi_pldadapt_rx_15_osc_clk_scg_en |
disable |
| hssi_pldadapt_rx_15_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_pldadapt_rx_15_pipe_enable |
disable |
| hssi_pldadapt_rx_15_pipe_mode |
disable_pipe |
| hssi_pldadapt_rx_15_hdpldadapt_pld_avmm1_clk_rowclk_hz |
0 |
| hssi_pldadapt_rx_15_hdpldadapt_pld_avmm2_clk_rowclk_hz |
0 |
| hssi_pldadapt_rx_15_pld_clk1_delay_en |
disable |
| hssi_pldadapt_rx_15_pld_clk1_delay_sel |
delay_path0 |
| hssi_pldadapt_rx_15_pld_clk1_inv_en |
disable |
| hssi_pldadapt_rx_15_pld_clk1_sel |
pld_clk1_rowclk |
| hssi_pldadapt_rx_15_hdpldadapt_pld_rx_clk1_dcm_hz |
0 |
| hssi_pldadapt_rx_15_hdpldadapt_pld_rx_clk1_rowclk_hz |
0 |
| hssi_pldadapt_rx_15_hdpldadapt_pld_sclk1_rowclk_hz |
0 |
| hssi_pldadapt_rx_15_hdpldadapt_pld_sclk2_rowclk_hz |
0 |
| hssi_pldadapt_rx_15_pma_hclk_scg_en |
disable |
| hssi_pldadapt_rx_15_powerdown_mode |
powerdown |
| hssi_pldadapt_rx_15_powermode_dc |
powerdown |
| hssi_pldadapt_rx_15_powermode_freq_hz_aib_fabric_rx_sr_clk_in |
0 |
| hssi_pldadapt_rx_15_powermode_freq_hz_pld_rx_clk1_dcm |
0 |
| hssi_pldadapt_rx_15_rx_datapath_tb_sel |
cp_bond |
| hssi_pldadapt_rx_15_rx_fastbond_rden |
rden_ds_del_us_del |
| hssi_pldadapt_rx_15_rx_fastbond_wren |
wren_ds_del_us_del |
| hssi_pldadapt_rx_15_rx_fifo_power_mode |
full_width_full_depth |
| hssi_pldadapt_rx_15_rx_fifo_read_latency_adjust |
disable |
| hssi_pldadapt_rx_15_rx_fifo_write_ctrl |
blklock_stops |
| hssi_pldadapt_rx_15_rx_fifo_write_latency_adjust |
disable |
| hssi_pldadapt_rx_15_rx_osc_clock_setting |
osc_clk_div_by1 |
| hssi_pldadapt_rx_15_rx_pld_8g_eidleinfersel_polling_bypass |
disable |
| hssi_pldadapt_rx_15_rx_pld_pma_eye_monitor_polling_bypass |
disable |
| hssi_pldadapt_rx_15_rx_pld_pma_pcie_switch_polling_bypass |
disable |
| hssi_pldadapt_rx_15_rx_pld_pma_reser_out_polling_bypass |
disable |
| hssi_pldadapt_rx_15_rx_prbs_flags_sr_enable |
disable |
| hssi_pldadapt_rx_15_rx_true_b2b |
b2b |
| hssi_pldadapt_rx_15_rx_usertest_sel |
enable |
| hssi_pldadapt_rx_15_rxfifo_empty |
empty_sw |
| hssi_pldadapt_rx_15_rxfifo_full |
full_pc_sw |
| hssi_pldadapt_rx_15_rxfifo_mode |
rxphase_comp |
| hssi_pldadapt_rx_15_rxfifo_pempty |
2 |
| hssi_pldadapt_rx_15_rxfifo_pfull |
48 |
| hssi_pldadapt_rx_15_rxfiford_post_ct_sel |
rxfiford_sclk_post_ct |
| hssi_pldadapt_rx_15_rxfifowr_post_ct_sel |
rxfifowr_sclk_post_ct |
| hssi_pldadapt_rx_15_sclk_sel |
sclk1_rowclk |
| hssi_pldadapt_rx_15_hdpldadapt_speed_grade |
dash_1 |
| hssi_pldadapt_rx_15_hdpldadapt_sr_sr_testbus_sel |
ssr_testbus |
| hssi_pldadapt_rx_15_stretch_num_stages |
zero_stage |
| hssi_pldadapt_rx_15_sup_mode |
user_mode |
| hssi_pldadapt_rx_15_txfiford_post_ct_sel |
txfiford_sclk_post_ct |
| hssi_pldadapt_rx_15_txfifowr_post_ct_sel |
txfifowr_sclk_post_ct |
| hssi_pldadapt_rx_15_us_bypass_pipeln |
us_bypass_pipeln_dis |
| hssi_pldadapt_rx_15_us_last_chnl |
us_not_last_chnl |
| hssi_pldadapt_rx_15_us_master |
us_master_en |
| hssi_pldadapt_rx_15_word_align |
wa_en |
| hssi_pldadapt_rx_15_word_align_enable |
disable |
| hssi_pldadapt_rx_15_silicon_rev |
14nm5 |
| hssi_pldadapt_rx_15_reconfig_settings |
{} |
| hssi_pldadapt_rx_23_aib_clk1_sel |
aib_clk1_rx_transfer_clk |
| hssi_pldadapt_rx_23_aib_clk2_sel |
aib_clk2_rx_transfer_clk |
| hssi_pldadapt_rx_23_hdpldadapt_aib_fabric_pld_pma_hclk_hz |
0 |
| hssi_pldadapt_rx_23_hdpldadapt_aib_fabric_rx_sr_clk_in_hz |
0 |
| hssi_pldadapt_rx_23_hdpldadapt_aib_fabric_rx_transfer_clk_hz |
0 |
| hssi_pldadapt_rx_23_asn_bypass_pma_pcie_sw_done |
disable |
| hssi_pldadapt_rx_23_asn_en |
disable |
| hssi_pldadapt_rx_23_asn_wait_for_dll_reset_cnt |
0 |
| hssi_pldadapt_rx_23_asn_wait_for_fifo_flush_cnt |
0 |
| hssi_pldadapt_rx_23_asn_wait_for_pma_pcie_sw_done_cnt |
0 |
| hssi_pldadapt_rx_23_bonding_dft_en |
dft_dis |
| hssi_pldadapt_rx_23_bonding_dft_val |
dft_0 |
| hssi_pldadapt_rx_23_chnl_bonding |
disable |
| hssi_pldadapt_rx_23_clock_del_measure_enable |
disable |
| hssi_pldadapt_rx_23_comp_cnt |
0 |
| hssi_pldadapt_rx_23_compin_sel |
compin_master |
| hssi_pldadapt_rx_23_hdpldadapt_csr_clk_hz |
0 |
| hssi_pldadapt_rx_23_ctrl_plane_bonding |
individual |
| hssi_pldadapt_rx_23_ds_bypass_pipeln |
ds_bypass_pipeln_dis |
| hssi_pldadapt_rx_23_ds_last_chnl |
ds_not_last_chnl |
| hssi_pldadapt_rx_23_ds_master |
ds_master_en |
| hssi_pldadapt_rx_23_duplex_mode |
disable |
| hssi_pldadapt_rx_23_dv_mode |
dv_mode_dis |
| hssi_pldadapt_rx_23_fifo_double_read |
fifo_double_read_dis |
| hssi_pldadapt_rx_23_fifo_mode |
phase_comp |
| hssi_pldadapt_rx_23_fifo_rd_clk_ins_sm_scg_en |
disable |
| hssi_pldadapt_rx_23_fifo_rd_clk_scg_en |
disable |
| hssi_pldadapt_rx_23_fifo_rd_clk_sel |
fifo_rd_clk_rx_transfer_clk |
| hssi_pldadapt_rx_23_fifo_stop_rd |
n_rd_empty |
| hssi_pldadapt_rx_23_fifo_stop_wr |
n_wr_full |
| hssi_pldadapt_rx_23_fifo_width |
fifo_single_width |
| hssi_pldadapt_rx_23_fifo_wr_clk_del_sm_scg_en |
disable |
| hssi_pldadapt_rx_23_fifo_wr_clk_scg_en |
disable |
| hssi_pldadapt_rx_23_fifo_wr_clk_sel |
fifo_wr_clk_rx_transfer_clk |
| hssi_pldadapt_rx_23_free_run_div_clk |
out_of_reset_sync |
| hssi_pldadapt_rx_23_fsr_pld_10g_rx_crc32_err_rst_val |
reset_to_zero_crc32 |
| hssi_pldadapt_rx_23_fsr_pld_8g_sigdet_out_rst_val |
reset_to_zero_sigdet |
| hssi_pldadapt_rx_23_fsr_pld_ltd_b_rst_val |
reset_to_zero_ltdb |
| hssi_pldadapt_rx_23_fsr_pld_ltr_rst_val |
reset_to_zero_ltr |
| hssi_pldadapt_rx_23_fsr_pld_rx_fifo_align_clr_rst_val |
reset_to_zero_alignclr |
| hssi_pldadapt_rx_23_gb_rx_idwidth |
idwidth_32 |
| hssi_pldadapt_rx_23_gb_rx_odwidth |
odwidth_66 |
| hssi_pldadapt_rx_23_hip_mode |
disable_hip |
| hssi_pldadapt_rx_23_hrdrst_align_bypass |
disable |
| hssi_pldadapt_rx_23_hrdrst_dll_lock_bypass |
disable |
| hssi_pldadapt_rx_23_hrdrst_rst_sm_dis |
enable_rx_rst_sm |
| hssi_pldadapt_rx_23_hrdrst_rx_osc_clk_scg_en |
disable |
| hssi_pldadapt_rx_23_hrdrst_user_ctl_en |
disable |
| hssi_pldadapt_rx_23_indv |
indv_en |
| hssi_pldadapt_rx_23_internal_clk1_sel1 |
pma_clks_or_txfiford_post_ct_mux_clk1_mux1 |
| hssi_pldadapt_rx_23_internal_clk1_sel2 |
pma_clks_clk1_mux2 |
| hssi_pldadapt_rx_23_internal_clk2_sel1 |
pma_clks_or_rxfifowr_post_ct_mux_clk2_mux1 |
| hssi_pldadapt_rx_23_internal_clk2_sel2 |
pma_clks_clk2_mux2 |
| hssi_pldadapt_rx_23_is_paired_with |
other |
| hssi_pldadapt_rx_23_loopback_mode |
disable |
| hssi_pldadapt_rx_23_low_latency_en |
disable |
| hssi_pldadapt_rx_23_lpbk_mode |
disable |
| hssi_pldadapt_rx_23_osc_clk_scg_en |
disable |
| hssi_pldadapt_rx_23_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_pldadapt_rx_23_pipe_enable |
disable |
| hssi_pldadapt_rx_23_pipe_mode |
disable_pipe |
| hssi_pldadapt_rx_23_hdpldadapt_pld_avmm1_clk_rowclk_hz |
0 |
| hssi_pldadapt_rx_23_hdpldadapt_pld_avmm2_clk_rowclk_hz |
0 |
| hssi_pldadapt_rx_23_pld_clk1_delay_en |
disable |
| hssi_pldadapt_rx_23_pld_clk1_delay_sel |
delay_path0 |
| hssi_pldadapt_rx_23_pld_clk1_inv_en |
disable |
| hssi_pldadapt_rx_23_pld_clk1_sel |
pld_clk1_rowclk |
| hssi_pldadapt_rx_23_hdpldadapt_pld_rx_clk1_dcm_hz |
0 |
| hssi_pldadapt_rx_23_hdpldadapt_pld_rx_clk1_rowclk_hz |
0 |
| hssi_pldadapt_rx_23_hdpldadapt_pld_sclk1_rowclk_hz |
0 |
| hssi_pldadapt_rx_23_hdpldadapt_pld_sclk2_rowclk_hz |
0 |
| hssi_pldadapt_rx_23_pma_hclk_scg_en |
disable |
| hssi_pldadapt_rx_23_powerdown_mode |
powerdown |
| hssi_pldadapt_rx_23_powermode_dc |
powerdown |
| hssi_pldadapt_rx_23_powermode_freq_hz_aib_fabric_rx_sr_clk_in |
0 |
| hssi_pldadapt_rx_23_powermode_freq_hz_pld_rx_clk1_dcm |
0 |
| hssi_pldadapt_rx_23_rx_datapath_tb_sel |
cp_bond |
| hssi_pldadapt_rx_23_rx_fastbond_rden |
rden_ds_del_us_del |
| hssi_pldadapt_rx_23_rx_fastbond_wren |
wren_ds_del_us_del |
| hssi_pldadapt_rx_23_rx_fifo_power_mode |
full_width_full_depth |
| hssi_pldadapt_rx_23_rx_fifo_read_latency_adjust |
disable |
| hssi_pldadapt_rx_23_rx_fifo_write_ctrl |
blklock_stops |
| hssi_pldadapt_rx_23_rx_fifo_write_latency_adjust |
disable |
| hssi_pldadapt_rx_23_rx_osc_clock_setting |
osc_clk_div_by1 |
| hssi_pldadapt_rx_23_rx_pld_8g_eidleinfersel_polling_bypass |
disable |
| hssi_pldadapt_rx_23_rx_pld_pma_eye_monitor_polling_bypass |
disable |
| hssi_pldadapt_rx_23_rx_pld_pma_pcie_switch_polling_bypass |
disable |
| hssi_pldadapt_rx_23_rx_pld_pma_reser_out_polling_bypass |
disable |
| hssi_pldadapt_rx_23_rx_prbs_flags_sr_enable |
disable |
| hssi_pldadapt_rx_23_rx_true_b2b |
b2b |
| hssi_pldadapt_rx_23_rx_usertest_sel |
enable |
| hssi_pldadapt_rx_23_rxfifo_empty |
empty_sw |
| hssi_pldadapt_rx_23_rxfifo_full |
full_pc_sw |
| hssi_pldadapt_rx_23_rxfifo_mode |
rxphase_comp |
| hssi_pldadapt_rx_23_rxfifo_pempty |
2 |
| hssi_pldadapt_rx_23_rxfifo_pfull |
48 |
| hssi_pldadapt_rx_23_rxfiford_post_ct_sel |
rxfiford_sclk_post_ct |
| hssi_pldadapt_rx_23_rxfifowr_post_ct_sel |
rxfifowr_sclk_post_ct |
| hssi_pldadapt_rx_23_sclk_sel |
sclk1_rowclk |
| hssi_pldadapt_rx_23_hdpldadapt_speed_grade |
dash_1 |
| hssi_pldadapt_rx_23_hdpldadapt_sr_sr_testbus_sel |
ssr_testbus |
| hssi_pldadapt_rx_23_stretch_num_stages |
zero_stage |
| hssi_pldadapt_rx_23_sup_mode |
user_mode |
| hssi_pldadapt_rx_23_txfiford_post_ct_sel |
txfiford_sclk_post_ct |
| hssi_pldadapt_rx_23_txfifowr_post_ct_sel |
txfifowr_sclk_post_ct |
| hssi_pldadapt_rx_23_us_bypass_pipeln |
us_bypass_pipeln_dis |
| hssi_pldadapt_rx_23_us_last_chnl |
us_not_last_chnl |
| hssi_pldadapt_rx_23_us_master |
us_master_en |
| hssi_pldadapt_rx_23_word_align |
wa_en |
| hssi_pldadapt_rx_23_word_align_enable |
disable |
| hssi_pldadapt_rx_23_silicon_rev |
14nm5 |
| hssi_pldadapt_rx_23_reconfig_settings |
{} |
| hssi_pldadapt_tx_0_aib_clk1_sel |
aib_clk1_pld_pcs_tx_clk_out |
| hssi_pldadapt_tx_0_aib_clk2_sel |
aib_clk2_pld_pcs_tx_clk_out |
| hssi_pldadapt_tx_0_hdpldadapt_aib_fabric_pld_pma_hclk_hz |
0 |
| hssi_pldadapt_tx_0_hdpldadapt_aib_fabric_pma_aib_tx_clk_hz |
0 |
| hssi_pldadapt_tx_0_hdpldadapt_aib_fabric_tx_sr_clk_in_hz |
0 |
| hssi_pldadapt_tx_0_bonding_dft_en |
dft_dis |
| hssi_pldadapt_tx_0_bonding_dft_val |
dft_0 |
| hssi_pldadapt_tx_0_chnl_bonding |
disable |
| hssi_pldadapt_tx_0_comp_cnt |
0 |
| hssi_pldadapt_tx_0_compin_sel |
compin_master |
| hssi_pldadapt_tx_0_hdpldadapt_csr_clk_hz |
0 |
| hssi_pldadapt_tx_0_ctrl_plane_bonding |
individual |
| hssi_pldadapt_tx_0_ds_bypass_pipeln |
ds_bypass_pipeln_dis |
| hssi_pldadapt_tx_0_ds_last_chnl |
ds_not_last_chnl |
| hssi_pldadapt_tx_0_ds_master |
ds_master_en |
| hssi_pldadapt_tx_0_duplex_mode |
disable |
| hssi_pldadapt_tx_0_dv_bond |
dv_bond_dis |
| hssi_pldadapt_tx_0_dv_gen |
dv_gen_dis |
| hssi_pldadapt_tx_0_fifo_double_write |
fifo_double_write_dis |
| hssi_pldadapt_tx_0_fifo_mode |
phase_comp |
| hssi_pldadapt_tx_0_fifo_rd_clk_frm_gen_scg_en |
disable |
| hssi_pldadapt_tx_0_fifo_rd_clk_scg_en |
disable |
| hssi_pldadapt_tx_0_fifo_rd_clk_sel |
fifo_rd_pma_aib_tx_clk |
| hssi_pldadapt_tx_0_fifo_stop_rd |
n_rd_empty |
| hssi_pldadapt_tx_0_fifo_stop_wr |
n_wr_full |
| hssi_pldadapt_tx_0_fifo_width |
fifo_single_width |
| hssi_pldadapt_tx_0_fifo_wr_clk_scg_en |
disable |
| hssi_pldadapt_tx_0_fpll_shared_direct_async_in_sel |
fpll_shared_direct_async_in_rowclk |
| hssi_pldadapt_tx_0_frmgen_burst |
frmgen_burst_dis |
| hssi_pldadapt_tx_0_frmgen_bypass |
frmgen_bypass_dis |
| hssi_pldadapt_tx_0_frmgen_mfrm_length |
2048 |
| hssi_pldadapt_tx_0_frmgen_pipeln |
frmgen_pipeln_dis |
| hssi_pldadapt_tx_0_frmgen_pyld_ins |
frmgen_pyld_ins_dis |
| hssi_pldadapt_tx_0_frmgen_wordslip |
frmgen_wordslip_dis |
| hssi_pldadapt_tx_0_fsr_hip_fsr_in_bit0_rst_val |
reset_to_zero_hfsrin0 |
| hssi_pldadapt_tx_0_fsr_hip_fsr_in_bit1_rst_val |
reset_to_zero_hfsrin1 |
| hssi_pldadapt_tx_0_fsr_hip_fsr_in_bit2_rst_val |
reset_to_zero_hfsrin2 |
| hssi_pldadapt_tx_0_fsr_hip_fsr_in_bit3_rst_val |
reset_to_zero_hfsrin3 |
| hssi_pldadapt_tx_0_fsr_hip_fsr_out_bit0_rst_val |
reset_to_zero_hfsrout0 |
| hssi_pldadapt_tx_0_fsr_hip_fsr_out_bit1_rst_val |
reset_to_zero_hfsrout1 |
| hssi_pldadapt_tx_0_fsr_hip_fsr_out_bit2_rst_val |
reset_to_zero_hfsrout2 |
| hssi_pldadapt_tx_0_fsr_hip_fsr_out_bit3_rst_val |
reset_to_zero_hfsrout3 |
| hssi_pldadapt_tx_0_fsr_mask_tx_pll_rst_val |
reset_to_zero_maskpll |
| hssi_pldadapt_tx_0_fsr_pld_txelecidle_rst_val |
reset_to_zero_txelec |
| hssi_pldadapt_tx_0_gb_tx_idwidth |
idwidth_66 |
| hssi_pldadapt_tx_0_gb_tx_odwidth |
odwidth_32 |
| hssi_pldadapt_tx_0_hip_mode |
disable_hip |
| hssi_pldadapt_tx_0_hip_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_0_hrdrst_dcd_cal_done_bypass |
disable |
| hssi_pldadapt_tx_0_hrdrst_rst_sm_dis |
enable_tx_rst_sm |
| hssi_pldadapt_tx_0_hrdrst_rx_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_0_hrdrst_user_ctl_en |
disable |
| hssi_pldadapt_tx_0_indv |
indv_en |
| hssi_pldadapt_tx_0_is_paired_with |
other |
| hssi_pldadapt_tx_0_loopback_mode |
disable |
| hssi_pldadapt_tx_0_low_latency_en |
disable |
| hssi_pldadapt_tx_0_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_0_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_pldadapt_tx_0_pipe_mode |
disable_pipe |
| hssi_pldadapt_tx_0_hdpldadapt_pld_avmm1_clk_rowclk_hz |
0 |
| hssi_pldadapt_tx_0_hdpldadapt_pld_avmm2_clk_rowclk_hz |
0 |
| hssi_pldadapt_tx_0_pld_clk1_delay_en |
disable |
| hssi_pldadapt_tx_0_pld_clk1_delay_sel |
delay_path0 |
| hssi_pldadapt_tx_0_pld_clk1_inv_en |
disable |
| hssi_pldadapt_tx_0_pld_clk1_sel |
pld_clk1_rowclk |
| hssi_pldadapt_tx_0_pld_clk2_sel |
pld_clk2_rowclk |
| hssi_pldadapt_tx_0_hdpldadapt_pld_sclk1_rowclk_hz |
0 |
| hssi_pldadapt_tx_0_hdpldadapt_pld_sclk2_rowclk_hz |
0 |
| hssi_pldadapt_tx_0_hdpldadapt_pld_tx_clk1_dcm_hz |
0 |
| hssi_pldadapt_tx_0_hdpldadapt_pld_tx_clk1_rowclk_hz |
0 |
| hssi_pldadapt_tx_0_hdpldadapt_pld_tx_clk2_dcm_hz |
0 |
| hssi_pldadapt_tx_0_hdpldadapt_pld_tx_clk2_rowclk_hz |
0 |
| hssi_pldadapt_tx_0_pma_aib_tx_clk_expected_setting |
not_used |
| hssi_pldadapt_tx_0_powerdown_mode |
powerdown |
| hssi_pldadapt_tx_0_powermode_dc |
powerdown |
| hssi_pldadapt_tx_0_powermode_freq_hz_aib_fabric_rx_sr_clk_in |
0 |
| hssi_pldadapt_tx_0_powermode_freq_hz_pld_tx_clk1_dcm |
0 |
| hssi_pldadapt_tx_0_sh_err |
sh_err_dis |
| hssi_pldadapt_tx_0_hdpldadapt_speed_grade |
dash_1 |
| hssi_pldadapt_tx_0_hdpldadapt_sr_sr_testbus_sel |
ssr_testbus |
| hssi_pldadapt_tx_0_stretch_num_stages |
zero_stage |
| hssi_pldadapt_tx_0_sup_mode |
user_mode |
| hssi_pldadapt_tx_0_tx_datapath_tb_sel |
cp_bond |
| hssi_pldadapt_tx_0_tx_fastbond_rden |
rden_ds_del_us_del |
| hssi_pldadapt_tx_0_tx_fastbond_wren |
wren_ds_del_us_del |
| hssi_pldadapt_tx_0_tx_fifo_power_mode |
full_width_full_depth |
| hssi_pldadapt_tx_0_tx_fifo_read_latency_adjust |
disable |
| hssi_pldadapt_tx_0_tx_fifo_write_latency_adjust |
disable |
| hssi_pldadapt_tx_0_tx_hip_aib_ssr_in_polling_bypass |
disable |
| hssi_pldadapt_tx_0_tx_osc_clock_setting |
osc_clk_div_by1 |
| hssi_pldadapt_tx_0_tx_pld_10g_tx_bitslip_polling_bypass |
disable |
| hssi_pldadapt_tx_0_tx_pld_8g_tx_boundary_sel_polling_bypass |
disable |
| hssi_pldadapt_tx_0_tx_pld_pma_fpll_cnt_sel_polling_bypass |
disable |
| hssi_pldadapt_tx_0_tx_pld_pma_fpll_num_phase_shifts_polling_bypass |
disable |
| hssi_pldadapt_tx_0_tx_usertest_sel |
enable |
| hssi_pldadapt_tx_0_txfifo_empty |
empty_default |
| hssi_pldadapt_tx_0_txfifo_full |
full_pc_sw |
| hssi_pldadapt_tx_0_txfifo_mode |
txphase_comp |
| hssi_pldadapt_tx_0_txfifo_pempty |
2 |
| hssi_pldadapt_tx_0_txfifo_pfull |
24 |
| hssi_pldadapt_tx_0_us_bypass_pipeln |
us_bypass_pipeln_dis |
| hssi_pldadapt_tx_0_us_last_chnl |
us_not_last_chnl |
| hssi_pldadapt_tx_0_us_master |
us_master_en |
| hssi_pldadapt_tx_0_word_align_enable |
disable |
| hssi_pldadapt_tx_0_word_mark |
wm_en |
| hssi_pldadapt_tx_0_silicon_rev |
14nm5 |
| hssi_pldadapt_tx_0_reconfig_settings |
{} |
| hssi_pldadapt_tx_13_aib_clk1_sel |
aib_clk1_pld_pcs_tx_clk_out |
| hssi_pldadapt_tx_13_aib_clk2_sel |
aib_clk2_pld_pcs_tx_clk_out |
| hssi_pldadapt_tx_13_hdpldadapt_aib_fabric_pld_pma_hclk_hz |
0 |
| hssi_pldadapt_tx_13_hdpldadapt_aib_fabric_pma_aib_tx_clk_hz |
0 |
| hssi_pldadapt_tx_13_hdpldadapt_aib_fabric_tx_sr_clk_in_hz |
0 |
| hssi_pldadapt_tx_13_bonding_dft_en |
dft_dis |
| hssi_pldadapt_tx_13_bonding_dft_val |
dft_0 |
| hssi_pldadapt_tx_13_chnl_bonding |
disable |
| hssi_pldadapt_tx_13_comp_cnt |
0 |
| hssi_pldadapt_tx_13_compin_sel |
compin_master |
| hssi_pldadapt_tx_13_hdpldadapt_csr_clk_hz |
0 |
| hssi_pldadapt_tx_13_ctrl_plane_bonding |
individual |
| hssi_pldadapt_tx_13_ds_bypass_pipeln |
ds_bypass_pipeln_dis |
| hssi_pldadapt_tx_13_ds_last_chnl |
ds_not_last_chnl |
| hssi_pldadapt_tx_13_ds_master |
ds_master_en |
| hssi_pldadapt_tx_13_duplex_mode |
disable |
| hssi_pldadapt_tx_13_dv_bond |
dv_bond_dis |
| hssi_pldadapt_tx_13_dv_gen |
dv_gen_dis |
| hssi_pldadapt_tx_13_fifo_double_write |
fifo_double_write_dis |
| hssi_pldadapt_tx_13_fifo_mode |
phase_comp |
| hssi_pldadapt_tx_13_fifo_rd_clk_frm_gen_scg_en |
disable |
| hssi_pldadapt_tx_13_fifo_rd_clk_scg_en |
disable |
| hssi_pldadapt_tx_13_fifo_rd_clk_sel |
fifo_rd_pma_aib_tx_clk |
| hssi_pldadapt_tx_13_fifo_stop_rd |
n_rd_empty |
| hssi_pldadapt_tx_13_fifo_stop_wr |
n_wr_full |
| hssi_pldadapt_tx_13_fifo_width |
fifo_single_width |
| hssi_pldadapt_tx_13_fifo_wr_clk_scg_en |
disable |
| hssi_pldadapt_tx_13_fpll_shared_direct_async_in_sel |
fpll_shared_direct_async_in_rowclk |
| hssi_pldadapt_tx_13_frmgen_burst |
frmgen_burst_dis |
| hssi_pldadapt_tx_13_frmgen_bypass |
frmgen_bypass_dis |
| hssi_pldadapt_tx_13_frmgen_mfrm_length |
2048 |
| hssi_pldadapt_tx_13_frmgen_pipeln |
frmgen_pipeln_dis |
| hssi_pldadapt_tx_13_frmgen_pyld_ins |
frmgen_pyld_ins_dis |
| hssi_pldadapt_tx_13_frmgen_wordslip |
frmgen_wordslip_dis |
| hssi_pldadapt_tx_13_fsr_hip_fsr_in_bit0_rst_val |
reset_to_zero_hfsrin0 |
| hssi_pldadapt_tx_13_fsr_hip_fsr_in_bit1_rst_val |
reset_to_zero_hfsrin1 |
| hssi_pldadapt_tx_13_fsr_hip_fsr_in_bit2_rst_val |
reset_to_zero_hfsrin2 |
| hssi_pldadapt_tx_13_fsr_hip_fsr_in_bit3_rst_val |
reset_to_zero_hfsrin3 |
| hssi_pldadapt_tx_13_fsr_hip_fsr_out_bit0_rst_val |
reset_to_zero_hfsrout0 |
| hssi_pldadapt_tx_13_fsr_hip_fsr_out_bit1_rst_val |
reset_to_zero_hfsrout1 |
| hssi_pldadapt_tx_13_fsr_hip_fsr_out_bit2_rst_val |
reset_to_zero_hfsrout2 |
| hssi_pldadapt_tx_13_fsr_hip_fsr_out_bit3_rst_val |
reset_to_zero_hfsrout3 |
| hssi_pldadapt_tx_13_fsr_mask_tx_pll_rst_val |
reset_to_zero_maskpll |
| hssi_pldadapt_tx_13_fsr_pld_txelecidle_rst_val |
reset_to_zero_txelec |
| hssi_pldadapt_tx_13_gb_tx_idwidth |
idwidth_66 |
| hssi_pldadapt_tx_13_gb_tx_odwidth |
odwidth_32 |
| hssi_pldadapt_tx_13_hip_mode |
disable_hip |
| hssi_pldadapt_tx_13_hip_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_13_hrdrst_dcd_cal_done_bypass |
disable |
| hssi_pldadapt_tx_13_hrdrst_rst_sm_dis |
enable_tx_rst_sm |
| hssi_pldadapt_tx_13_hrdrst_rx_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_13_hrdrst_user_ctl_en |
disable |
| hssi_pldadapt_tx_13_indv |
indv_en |
| hssi_pldadapt_tx_13_is_paired_with |
other |
| hssi_pldadapt_tx_13_loopback_mode |
disable |
| hssi_pldadapt_tx_13_low_latency_en |
disable |
| hssi_pldadapt_tx_13_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_13_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_pldadapt_tx_13_pipe_mode |
disable_pipe |
| hssi_pldadapt_tx_13_hdpldadapt_pld_avmm1_clk_rowclk_hz |
0 |
| hssi_pldadapt_tx_13_hdpldadapt_pld_avmm2_clk_rowclk_hz |
0 |
| hssi_pldadapt_tx_13_pld_clk1_delay_en |
disable |
| hssi_pldadapt_tx_13_pld_clk1_delay_sel |
delay_path0 |
| hssi_pldadapt_tx_13_pld_clk1_inv_en |
disable |
| hssi_pldadapt_tx_13_pld_clk1_sel |
pld_clk1_rowclk |
| hssi_pldadapt_tx_13_pld_clk2_sel |
pld_clk2_rowclk |
| hssi_pldadapt_tx_13_hdpldadapt_pld_sclk1_rowclk_hz |
0 |
| hssi_pldadapt_tx_13_hdpldadapt_pld_sclk2_rowclk_hz |
0 |
| hssi_pldadapt_tx_13_hdpldadapt_pld_tx_clk1_dcm_hz |
0 |
| hssi_pldadapt_tx_13_hdpldadapt_pld_tx_clk1_rowclk_hz |
0 |
| hssi_pldadapt_tx_13_hdpldadapt_pld_tx_clk2_dcm_hz |
0 |
| hssi_pldadapt_tx_13_hdpldadapt_pld_tx_clk2_rowclk_hz |
0 |
| hssi_pldadapt_tx_13_pma_aib_tx_clk_expected_setting |
not_used |
| hssi_pldadapt_tx_13_powerdown_mode |
powerdown |
| hssi_pldadapt_tx_13_powermode_dc |
powerdown |
| hssi_pldadapt_tx_13_powermode_freq_hz_aib_fabric_rx_sr_clk_in |
0 |
| hssi_pldadapt_tx_13_powermode_freq_hz_pld_tx_clk1_dcm |
0 |
| hssi_pldadapt_tx_13_sh_err |
sh_err_dis |
| hssi_pldadapt_tx_13_hdpldadapt_speed_grade |
dash_1 |
| hssi_pldadapt_tx_13_hdpldadapt_sr_sr_testbus_sel |
ssr_testbus |
| hssi_pldadapt_tx_13_stretch_num_stages |
zero_stage |
| hssi_pldadapt_tx_13_sup_mode |
user_mode |
| hssi_pldadapt_tx_13_tx_datapath_tb_sel |
cp_bond |
| hssi_pldadapt_tx_13_tx_fastbond_rden |
rden_ds_del_us_del |
| hssi_pldadapt_tx_13_tx_fastbond_wren |
wren_ds_del_us_del |
| hssi_pldadapt_tx_13_tx_fifo_power_mode |
full_width_full_depth |
| hssi_pldadapt_tx_13_tx_fifo_read_latency_adjust |
disable |
| hssi_pldadapt_tx_13_tx_fifo_write_latency_adjust |
disable |
| hssi_pldadapt_tx_13_tx_hip_aib_ssr_in_polling_bypass |
disable |
| hssi_pldadapt_tx_13_tx_osc_clock_setting |
osc_clk_div_by1 |
| hssi_pldadapt_tx_13_tx_pld_10g_tx_bitslip_polling_bypass |
disable |
| hssi_pldadapt_tx_13_tx_pld_8g_tx_boundary_sel_polling_bypass |
disable |
| hssi_pldadapt_tx_13_tx_pld_pma_fpll_cnt_sel_polling_bypass |
disable |
| hssi_pldadapt_tx_13_tx_pld_pma_fpll_num_phase_shifts_polling_bypass |
disable |
| hssi_pldadapt_tx_13_tx_usertest_sel |
enable |
| hssi_pldadapt_tx_13_txfifo_empty |
empty_default |
| hssi_pldadapt_tx_13_txfifo_full |
full_pc_sw |
| hssi_pldadapt_tx_13_txfifo_mode |
txphase_comp |
| hssi_pldadapt_tx_13_txfifo_pempty |
2 |
| hssi_pldadapt_tx_13_txfifo_pfull |
24 |
| hssi_pldadapt_tx_13_us_bypass_pipeln |
us_bypass_pipeln_dis |
| hssi_pldadapt_tx_13_us_last_chnl |
us_not_last_chnl |
| hssi_pldadapt_tx_13_us_master |
us_master_en |
| hssi_pldadapt_tx_13_word_align_enable |
disable |
| hssi_pldadapt_tx_13_word_mark |
wm_en |
| hssi_pldadapt_tx_13_silicon_rev |
14nm5 |
| hssi_pldadapt_tx_13_reconfig_settings |
{} |
| hssi_pldadapt_tx_15_aib_clk1_sel |
aib_clk1_pld_pcs_tx_clk_out |
| hssi_pldadapt_tx_15_aib_clk2_sel |
aib_clk2_pld_pcs_tx_clk_out |
| hssi_pldadapt_tx_15_hdpldadapt_aib_fabric_pld_pma_hclk_hz |
0 |
| hssi_pldadapt_tx_15_hdpldadapt_aib_fabric_pma_aib_tx_clk_hz |
0 |
| hssi_pldadapt_tx_15_hdpldadapt_aib_fabric_tx_sr_clk_in_hz |
0 |
| hssi_pldadapt_tx_15_bonding_dft_en |
dft_dis |
| hssi_pldadapt_tx_15_bonding_dft_val |
dft_0 |
| hssi_pldadapt_tx_15_chnl_bonding |
disable |
| hssi_pldadapt_tx_15_comp_cnt |
0 |
| hssi_pldadapt_tx_15_compin_sel |
compin_master |
| hssi_pldadapt_tx_15_hdpldadapt_csr_clk_hz |
0 |
| hssi_pldadapt_tx_15_ctrl_plane_bonding |
individual |
| hssi_pldadapt_tx_15_ds_bypass_pipeln |
ds_bypass_pipeln_dis |
| hssi_pldadapt_tx_15_ds_last_chnl |
ds_not_last_chnl |
| hssi_pldadapt_tx_15_ds_master |
ds_master_en |
| hssi_pldadapt_tx_15_duplex_mode |
disable |
| hssi_pldadapt_tx_15_dv_bond |
dv_bond_dis |
| hssi_pldadapt_tx_15_dv_gen |
dv_gen_dis |
| hssi_pldadapt_tx_15_fifo_double_write |
fifo_double_write_dis |
| hssi_pldadapt_tx_15_fifo_mode |
phase_comp |
| hssi_pldadapt_tx_15_fifo_rd_clk_frm_gen_scg_en |
disable |
| hssi_pldadapt_tx_15_fifo_rd_clk_scg_en |
disable |
| hssi_pldadapt_tx_15_fifo_rd_clk_sel |
fifo_rd_pma_aib_tx_clk |
| hssi_pldadapt_tx_15_fifo_stop_rd |
n_rd_empty |
| hssi_pldadapt_tx_15_fifo_stop_wr |
n_wr_full |
| hssi_pldadapt_tx_15_fifo_width |
fifo_single_width |
| hssi_pldadapt_tx_15_fifo_wr_clk_scg_en |
disable |
| hssi_pldadapt_tx_15_fpll_shared_direct_async_in_sel |
fpll_shared_direct_async_in_rowclk |
| hssi_pldadapt_tx_15_frmgen_burst |
frmgen_burst_dis |
| hssi_pldadapt_tx_15_frmgen_bypass |
frmgen_bypass_dis |
| hssi_pldadapt_tx_15_frmgen_mfrm_length |
2048 |
| hssi_pldadapt_tx_15_frmgen_pipeln |
frmgen_pipeln_dis |
| hssi_pldadapt_tx_15_frmgen_pyld_ins |
frmgen_pyld_ins_dis |
| hssi_pldadapt_tx_15_frmgen_wordslip |
frmgen_wordslip_dis |
| hssi_pldadapt_tx_15_fsr_hip_fsr_in_bit0_rst_val |
reset_to_zero_hfsrin0 |
| hssi_pldadapt_tx_15_fsr_hip_fsr_in_bit1_rst_val |
reset_to_zero_hfsrin1 |
| hssi_pldadapt_tx_15_fsr_hip_fsr_in_bit2_rst_val |
reset_to_zero_hfsrin2 |
| hssi_pldadapt_tx_15_fsr_hip_fsr_in_bit3_rst_val |
reset_to_zero_hfsrin3 |
| hssi_pldadapt_tx_15_fsr_hip_fsr_out_bit0_rst_val |
reset_to_zero_hfsrout0 |
| hssi_pldadapt_tx_15_fsr_hip_fsr_out_bit1_rst_val |
reset_to_zero_hfsrout1 |
| hssi_pldadapt_tx_15_fsr_hip_fsr_out_bit2_rst_val |
reset_to_zero_hfsrout2 |
| hssi_pldadapt_tx_15_fsr_hip_fsr_out_bit3_rst_val |
reset_to_zero_hfsrout3 |
| hssi_pldadapt_tx_15_fsr_mask_tx_pll_rst_val |
reset_to_zero_maskpll |
| hssi_pldadapt_tx_15_fsr_pld_txelecidle_rst_val |
reset_to_zero_txelec |
| hssi_pldadapt_tx_15_gb_tx_idwidth |
idwidth_66 |
| hssi_pldadapt_tx_15_gb_tx_odwidth |
odwidth_32 |
| hssi_pldadapt_tx_15_hip_mode |
disable_hip |
| hssi_pldadapt_tx_15_hip_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_15_hrdrst_dcd_cal_done_bypass |
disable |
| hssi_pldadapt_tx_15_hrdrst_rst_sm_dis |
enable_tx_rst_sm |
| hssi_pldadapt_tx_15_hrdrst_rx_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_15_hrdrst_user_ctl_en |
disable |
| hssi_pldadapt_tx_15_indv |
indv_en |
| hssi_pldadapt_tx_15_is_paired_with |
other |
| hssi_pldadapt_tx_15_loopback_mode |
disable |
| hssi_pldadapt_tx_15_low_latency_en |
disable |
| hssi_pldadapt_tx_15_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_15_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_pldadapt_tx_15_pipe_mode |
disable_pipe |
| hssi_pldadapt_tx_15_hdpldadapt_pld_avmm1_clk_rowclk_hz |
0 |
| hssi_pldadapt_tx_15_hdpldadapt_pld_avmm2_clk_rowclk_hz |
0 |
| hssi_pldadapt_tx_15_pld_clk1_delay_en |
disable |
| hssi_pldadapt_tx_15_pld_clk1_delay_sel |
delay_path0 |
| hssi_pldadapt_tx_15_pld_clk1_inv_en |
disable |
| hssi_pldadapt_tx_15_pld_clk1_sel |
pld_clk1_rowclk |
| hssi_pldadapt_tx_15_pld_clk2_sel |
pld_clk2_rowclk |
| hssi_pldadapt_tx_15_hdpldadapt_pld_sclk1_rowclk_hz |
0 |
| hssi_pldadapt_tx_15_hdpldadapt_pld_sclk2_rowclk_hz |
0 |
| hssi_pldadapt_tx_15_hdpldadapt_pld_tx_clk1_dcm_hz |
0 |
| hssi_pldadapt_tx_15_hdpldadapt_pld_tx_clk1_rowclk_hz |
0 |
| hssi_pldadapt_tx_15_hdpldadapt_pld_tx_clk2_dcm_hz |
0 |
| hssi_pldadapt_tx_15_hdpldadapt_pld_tx_clk2_rowclk_hz |
0 |
| hssi_pldadapt_tx_15_pma_aib_tx_clk_expected_setting |
not_used |
| hssi_pldadapt_tx_15_powerdown_mode |
powerdown |
| hssi_pldadapt_tx_15_powermode_dc |
powerdown |
| hssi_pldadapt_tx_15_powermode_freq_hz_aib_fabric_rx_sr_clk_in |
0 |
| hssi_pldadapt_tx_15_powermode_freq_hz_pld_tx_clk1_dcm |
0 |
| hssi_pldadapt_tx_15_sh_err |
sh_err_dis |
| hssi_pldadapt_tx_15_hdpldadapt_speed_grade |
dash_1 |
| hssi_pldadapt_tx_15_hdpldadapt_sr_sr_testbus_sel |
ssr_testbus |
| hssi_pldadapt_tx_15_stretch_num_stages |
zero_stage |
| hssi_pldadapt_tx_15_sup_mode |
user_mode |
| hssi_pldadapt_tx_15_tx_datapath_tb_sel |
cp_bond |
| hssi_pldadapt_tx_15_tx_fastbond_rden |
rden_ds_del_us_del |
| hssi_pldadapt_tx_15_tx_fastbond_wren |
wren_ds_del_us_del |
| hssi_pldadapt_tx_15_tx_fifo_power_mode |
full_width_full_depth |
| hssi_pldadapt_tx_15_tx_fifo_read_latency_adjust |
disable |
| hssi_pldadapt_tx_15_tx_fifo_write_latency_adjust |
disable |
| hssi_pldadapt_tx_15_tx_hip_aib_ssr_in_polling_bypass |
disable |
| hssi_pldadapt_tx_15_tx_osc_clock_setting |
osc_clk_div_by1 |
| hssi_pldadapt_tx_15_tx_pld_10g_tx_bitslip_polling_bypass |
disable |
| hssi_pldadapt_tx_15_tx_pld_8g_tx_boundary_sel_polling_bypass |
disable |
| hssi_pldadapt_tx_15_tx_pld_pma_fpll_cnt_sel_polling_bypass |
disable |
| hssi_pldadapt_tx_15_tx_pld_pma_fpll_num_phase_shifts_polling_bypass |
disable |
| hssi_pldadapt_tx_15_tx_usertest_sel |
enable |
| hssi_pldadapt_tx_15_txfifo_empty |
empty_default |
| hssi_pldadapt_tx_15_txfifo_full |
full_pc_sw |
| hssi_pldadapt_tx_15_txfifo_mode |
txphase_comp |
| hssi_pldadapt_tx_15_txfifo_pempty |
2 |
| hssi_pldadapt_tx_15_txfifo_pfull |
24 |
| hssi_pldadapt_tx_15_us_bypass_pipeln |
us_bypass_pipeln_dis |
| hssi_pldadapt_tx_15_us_last_chnl |
us_not_last_chnl |
| hssi_pldadapt_tx_15_us_master |
us_master_en |
| hssi_pldadapt_tx_15_word_align_enable |
disable |
| hssi_pldadapt_tx_15_word_mark |
wm_en |
| hssi_pldadapt_tx_15_silicon_rev |
14nm5 |
| hssi_pldadapt_tx_15_reconfig_settings |
{} |
| hssi_pldadapt_tx_23_aib_clk1_sel |
aib_clk1_pld_pcs_tx_clk_out |
| hssi_pldadapt_tx_23_aib_clk2_sel |
aib_clk2_pld_pcs_tx_clk_out |
| hssi_pldadapt_tx_23_hdpldadapt_aib_fabric_pld_pma_hclk_hz |
0 |
| hssi_pldadapt_tx_23_hdpldadapt_aib_fabric_pma_aib_tx_clk_hz |
0 |
| hssi_pldadapt_tx_23_hdpldadapt_aib_fabric_tx_sr_clk_in_hz |
0 |
| hssi_pldadapt_tx_23_bonding_dft_en |
dft_dis |
| hssi_pldadapt_tx_23_bonding_dft_val |
dft_0 |
| hssi_pldadapt_tx_23_chnl_bonding |
disable |
| hssi_pldadapt_tx_23_comp_cnt |
0 |
| hssi_pldadapt_tx_23_compin_sel |
compin_master |
| hssi_pldadapt_tx_23_hdpldadapt_csr_clk_hz |
0 |
| hssi_pldadapt_tx_23_ctrl_plane_bonding |
individual |
| hssi_pldadapt_tx_23_ds_bypass_pipeln |
ds_bypass_pipeln_dis |
| hssi_pldadapt_tx_23_ds_last_chnl |
ds_not_last_chnl |
| hssi_pldadapt_tx_23_ds_master |
ds_master_en |
| hssi_pldadapt_tx_23_duplex_mode |
disable |
| hssi_pldadapt_tx_23_dv_bond |
dv_bond_dis |
| hssi_pldadapt_tx_23_dv_gen |
dv_gen_dis |
| hssi_pldadapt_tx_23_fifo_double_write |
fifo_double_write_dis |
| hssi_pldadapt_tx_23_fifo_mode |
phase_comp |
| hssi_pldadapt_tx_23_fifo_rd_clk_frm_gen_scg_en |
disable |
| hssi_pldadapt_tx_23_fifo_rd_clk_scg_en |
disable |
| hssi_pldadapt_tx_23_fifo_rd_clk_sel |
fifo_rd_pma_aib_tx_clk |
| hssi_pldadapt_tx_23_fifo_stop_rd |
n_rd_empty |
| hssi_pldadapt_tx_23_fifo_stop_wr |
n_wr_full |
| hssi_pldadapt_tx_23_fifo_width |
fifo_single_width |
| hssi_pldadapt_tx_23_fifo_wr_clk_scg_en |
disable |
| hssi_pldadapt_tx_23_fpll_shared_direct_async_in_sel |
fpll_shared_direct_async_in_rowclk |
| hssi_pldadapt_tx_23_frmgen_burst |
frmgen_burst_dis |
| hssi_pldadapt_tx_23_frmgen_bypass |
frmgen_bypass_dis |
| hssi_pldadapt_tx_23_frmgen_mfrm_length |
2048 |
| hssi_pldadapt_tx_23_frmgen_pipeln |
frmgen_pipeln_dis |
| hssi_pldadapt_tx_23_frmgen_pyld_ins |
frmgen_pyld_ins_dis |
| hssi_pldadapt_tx_23_frmgen_wordslip |
frmgen_wordslip_dis |
| hssi_pldadapt_tx_23_fsr_hip_fsr_in_bit0_rst_val |
reset_to_zero_hfsrin0 |
| hssi_pldadapt_tx_23_fsr_hip_fsr_in_bit1_rst_val |
reset_to_zero_hfsrin1 |
| hssi_pldadapt_tx_23_fsr_hip_fsr_in_bit2_rst_val |
reset_to_zero_hfsrin2 |
| hssi_pldadapt_tx_23_fsr_hip_fsr_in_bit3_rst_val |
reset_to_zero_hfsrin3 |
| hssi_pldadapt_tx_23_fsr_hip_fsr_out_bit0_rst_val |
reset_to_zero_hfsrout0 |
| hssi_pldadapt_tx_23_fsr_hip_fsr_out_bit1_rst_val |
reset_to_zero_hfsrout1 |
| hssi_pldadapt_tx_23_fsr_hip_fsr_out_bit2_rst_val |
reset_to_zero_hfsrout2 |
| hssi_pldadapt_tx_23_fsr_hip_fsr_out_bit3_rst_val |
reset_to_zero_hfsrout3 |
| hssi_pldadapt_tx_23_fsr_mask_tx_pll_rst_val |
reset_to_zero_maskpll |
| hssi_pldadapt_tx_23_fsr_pld_txelecidle_rst_val |
reset_to_zero_txelec |
| hssi_pldadapt_tx_23_gb_tx_idwidth |
idwidth_66 |
| hssi_pldadapt_tx_23_gb_tx_odwidth |
odwidth_32 |
| hssi_pldadapt_tx_23_hip_mode |
disable_hip |
| hssi_pldadapt_tx_23_hip_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_23_hrdrst_dcd_cal_done_bypass |
disable |
| hssi_pldadapt_tx_23_hrdrst_rst_sm_dis |
enable_tx_rst_sm |
| hssi_pldadapt_tx_23_hrdrst_rx_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_23_hrdrst_user_ctl_en |
disable |
| hssi_pldadapt_tx_23_indv |
indv_en |
| hssi_pldadapt_tx_23_is_paired_with |
other |
| hssi_pldadapt_tx_23_loopback_mode |
disable |
| hssi_pldadapt_tx_23_low_latency_en |
disable |
| hssi_pldadapt_tx_23_osc_clk_scg_en |
disable |
| hssi_pldadapt_tx_23_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_pldadapt_tx_23_pipe_mode |
disable_pipe |
| hssi_pldadapt_tx_23_hdpldadapt_pld_avmm1_clk_rowclk_hz |
0 |
| hssi_pldadapt_tx_23_hdpldadapt_pld_avmm2_clk_rowclk_hz |
0 |
| hssi_pldadapt_tx_23_pld_clk1_delay_en |
disable |
| hssi_pldadapt_tx_23_pld_clk1_delay_sel |
delay_path0 |
| hssi_pldadapt_tx_23_pld_clk1_inv_en |
disable |
| hssi_pldadapt_tx_23_pld_clk1_sel |
pld_clk1_rowclk |
| hssi_pldadapt_tx_23_pld_clk2_sel |
pld_clk2_rowclk |
| hssi_pldadapt_tx_23_hdpldadapt_pld_sclk1_rowclk_hz |
0 |
| hssi_pldadapt_tx_23_hdpldadapt_pld_sclk2_rowclk_hz |
0 |
| hssi_pldadapt_tx_23_hdpldadapt_pld_tx_clk1_dcm_hz |
0 |
| hssi_pldadapt_tx_23_hdpldadapt_pld_tx_clk1_rowclk_hz |
0 |
| hssi_pldadapt_tx_23_hdpldadapt_pld_tx_clk2_dcm_hz |
0 |
| hssi_pldadapt_tx_23_hdpldadapt_pld_tx_clk2_rowclk_hz |
0 |
| hssi_pldadapt_tx_23_pma_aib_tx_clk_expected_setting |
not_used |
| hssi_pldadapt_tx_23_powerdown_mode |
powerdown |
| hssi_pldadapt_tx_23_powermode_dc |
powerdown |
| hssi_pldadapt_tx_23_powermode_freq_hz_aib_fabric_rx_sr_clk_in |
0 |
| hssi_pldadapt_tx_23_powermode_freq_hz_pld_tx_clk1_dcm |
0 |
| hssi_pldadapt_tx_23_sh_err |
sh_err_dis |
| hssi_pldadapt_tx_23_hdpldadapt_speed_grade |
dash_1 |
| hssi_pldadapt_tx_23_hdpldadapt_sr_sr_testbus_sel |
ssr_testbus |
| hssi_pldadapt_tx_23_stretch_num_stages |
zero_stage |
| hssi_pldadapt_tx_23_sup_mode |
user_mode |
| hssi_pldadapt_tx_23_tx_datapath_tb_sel |
cp_bond |
| hssi_pldadapt_tx_23_tx_fastbond_rden |
rden_ds_del_us_del |
| hssi_pldadapt_tx_23_tx_fastbond_wren |
wren_ds_del_us_del |
| hssi_pldadapt_tx_23_tx_fifo_power_mode |
full_width_full_depth |
| hssi_pldadapt_tx_23_tx_fifo_read_latency_adjust |
disable |
| hssi_pldadapt_tx_23_tx_fifo_write_latency_adjust |
disable |
| hssi_pldadapt_tx_23_tx_hip_aib_ssr_in_polling_bypass |
disable |
| hssi_pldadapt_tx_23_tx_osc_clock_setting |
osc_clk_div_by1 |
| hssi_pldadapt_tx_23_tx_pld_10g_tx_bitslip_polling_bypass |
disable |
| hssi_pldadapt_tx_23_tx_pld_8g_tx_boundary_sel_polling_bypass |
disable |
| hssi_pldadapt_tx_23_tx_pld_pma_fpll_cnt_sel_polling_bypass |
disable |
| hssi_pldadapt_tx_23_tx_pld_pma_fpll_num_phase_shifts_polling_bypass |
disable |
| hssi_pldadapt_tx_23_tx_usertest_sel |
enable |
| hssi_pldadapt_tx_23_txfifo_empty |
empty_default |
| hssi_pldadapt_tx_23_txfifo_full |
full_pc_sw |
| hssi_pldadapt_tx_23_txfifo_mode |
txphase_comp |
| hssi_pldadapt_tx_23_txfifo_pempty |
2 |
| hssi_pldadapt_tx_23_txfifo_pfull |
24 |
| hssi_pldadapt_tx_23_us_bypass_pipeln |
us_bypass_pipeln_dis |
| hssi_pldadapt_tx_23_us_last_chnl |
us_not_last_chnl |
| hssi_pldadapt_tx_23_us_master |
us_master_en |
| hssi_pldadapt_tx_23_word_align_enable |
disable |
| hssi_pldadapt_tx_23_word_mark |
wm_en |
| hssi_pldadapt_tx_23_silicon_rev |
14nm5 |
| hssi_pldadapt_tx_23_reconfig_settings |
{} |
| hssi_ctr_active_lane_octet0 |
octet0_lane_8on |
| hssi_ctr_active_lane_octet1 |
octet1_lane_8on |
| hssi_ctr_htol |
disable |
| hssi_ctr_independent_pcie_x8x8 |
disable |
| hssi_ctr_iopads_powerdown_mode |
true |
| hssi_ctr_is_cvp_enable |
false |
| hssi_ctr_pcie_capable |
gen5_capable |
| hssi_ctr_pcie_p0_config |
p0_rp |
| hssi_ctr_pcie_p1_config |
p1_rp |
| hssi_ctr_pcie_p2_config |
p2_rp |
| hssi_ctr_pcie_p3_config |
p3_rp |
| hssi_ctr_pcie_pld_data_width |
wide |
| hssi_ctr_pcie_virt_aspm |
no_aspm |
| hssi_ctr_pipe_direct_octet0 |
octet0_eight_x1 |
| hssi_ctr_pipe_direct_octet1 |
octet1_eight_x1 |
| hssi_ctr_pld_txrx_clk_hz |
pld_1000mhz |
| hssi_ctr_powerdown_mode |
true |
| hssi_ctr_sup_mode |
user_mode |
| hssi_ctr_topology |
pcie_x16 |
| hssi_ctr_true_independent_support_mode |
disable |
| hssi_ctr_u_aib_top_powerdown_mode |
true |
| hssi_ctr_u_aib_top_sup_mode |
user_mode |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_0_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_10_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_11_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_12_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_13_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_14_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_15_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_16_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_17_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_18_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_19_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_1_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_20_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_21_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_22_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_23_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_2_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_3_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_4_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_5_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_6_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_7_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_8_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_avmm_avmm_testbus_sel |
avmm1_transfer_testbus |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_rxchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_rxchnl_internal_clk1_sel |
feedthru_clk0_clk1 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_rxchnl_internal_clk2_sel |
feedthru_clk0_clk2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_rxchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_rxchnl_rx_datapath_tb_sel |
pcs_chnl_tb |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_rxchnl_rx_pcs_testbus_sel |
direct_tr_tb_bit0_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_rxchnl_rx_pma_div2_clk_sel |
phy_rx_word_clk |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_rxchnl_rx_ssr_tb_sel |
sel_i_chnl_ssr |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_rxchnl_rx_usertest_sel |
direct_tr_usertest3_sel |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_rxchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_sr_sr_osc_clk_div_sel |
non_div |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_txchnl_hrdrst_user_ctl_en |
disable |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_txchnl_phcomp_rd_del |
phcomp_rd_del2 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_txchnl_stretch_num_stages |
zero_stage |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_adapter_txchnl_tx_datapath_tb_sel |
cp_bond |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_dfd_data_sel_grp0 |
tx_fifo_wrptr_wrdata_0to27_prbs |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_dfd_data_sel_grp1 |
tx_fifo_rdptr_rddata_0to27_premap |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_dfd_data_sel_grp2 |
rx_fifo_rdptr_rddata_0to27_postloopback |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_dfd_data_sel_grp3 |
rx_fifo_wrpt_wrdata_0to27 |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_dfd_reset_n |
dfd_register_reset_asserted |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_dfd_trigger0_sel_grp0 |
tx_fifo_wa_lock |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_dfd_trigger0_sel_grp1 |
tx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_dfd_trigger0_sel_grp2 |
rx_fifo_rd_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_dfd_trigger0_sel_grp3 |
rx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibadapter_dfd_trigger1_sel_grp0 |
tx_fifo_wr_en |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibchl_top_wrp_xrnr_aibchl_top_xrxdatapath_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dfd_dll_dcc_en |
disable_dfd |
| hssi_ctr_u_aib_top_u_aibadapt_wrap_9_rnr_aibchl_top_wrp_xrnr_aibchl_top_xtxdatapath_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_async_direct_rx_sel |
254 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_byp_mode |
hrc_mode |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_bypass_ctrl_0_control |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_bypass_ctrl_1_control |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_bypass_ctrl_2_control |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_bypass_irq_msk |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_cfg_pldpll_disable |
enable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_cfg_second_pipepll_en |
disable_2nd |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_cfg_sel_reset_assert |
pll_lock_assert |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_cfg_sel_reset_deassert |
pll_lock_deassert |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_cold_reset_time |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_core_rst_width |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_cpll_post_rls_quiet_time |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_cpll_post_rst_quiet_time |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_dfd_mux_adpt_0to7 |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_dfd_mux_adpt_16to23 |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_dfd_mux_adpt_8to15 |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_dfd_mux_hrc |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_dfd_pattern_cntr_data_sel |
user_data |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_dfd_reset_n |
reset_en |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_dis_chkplllock_b4_corerst |
disable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_dis_phystatchk_b4_partialrst |
disable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_disable_phy_timer |
enable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_enable_phy_status |
enable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_error_irq_msk |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_hrc_dfd_grp0_sel |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_hrc_dfd_grp1_sel |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_hrc_dfd_grp2_sel |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_hrc_dfd_grp3_sel |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_lane_rls_quiet_time |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_lane_stagger_disable |
enable_lane_reset_staggering |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_lane_stagger_interval |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_linkreq_fullrst |
disable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_linkreq_partialrst |
disable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_octet_cfg_en |
disable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_perst_hi_filt_time |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_perst_lo_filt_time |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_phy_lane_rst_width |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_phy_post_lane_rst_quiet_time |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_pin_perst0_is_fullrst |
disable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_pin_perst1_is_fullrst |
disable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_pin_perst_is_full_rst |
full_reset |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_pipepll_error_timeout |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_pldpll_error_timeout |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_pldpll_rsten_warm |
disable |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_post_core_rst_quiet_time |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_sideband_clksel |
sideband_div8clk |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_warm_rst_timeout |
0 |
| hssi_ctr_u_aib_top_u_rnr_aib_cmn_u_rnr_hrc_top_warm_rst_timeout_prescaler |
0 |
| hssi_ctr_u_ctrl_powerdown_mode |
true |
| hssi_ctr_u_ctrl_toolkit_debug_mode |
toolkit_debug_mode_disable |
| hssi_ctr_u_ial_top_cxl_op_mode |
io_only |
| hssi_ctr_u_ial_top_r_credit_return_scheme |
rel_cnt |
| hssi_ctr_u_ial_top_r_cxlio_dphy_send_lidl_en_dis |
r_cxlio_dphy_send_lidl_en_dis_false |
| hssi_ctr_u_ial_top_r_flp_phy_rcvd_ts2_all_lanes_dis |
r_flp_phy_rcvd_ts2_all_lanes_dis_false |
| hssi_ctr_u_ial_top_r_s2m_drs_bypass_disrepflithdr |
r_s2m_drs_bypass_disrepflithdr_false |
| hssi_ctr_u_ial_top_r_wptr_delay |
one_cycle |
| hssi_ctr_u_ial_top_rnr_ialup_flp_inst_flxbusptctl_driftbuf_en |
flxbusptctl_driftbuf_en_false |
| hssi_ctr_u_ial_top_rnr_ialup_flp_inst_hybrid_x4_width |
disable_x4 |
| hssi_ctr_u_ial_top_rnr_ialup_flp_inst_iapctl2_ialinvratelnkdn |
iapctl2_ialinvratelnkdn_false |
| hssi_ctr_u_ial_top_rnr_ialup_flp_inst_iapctl2_vid |
32902 |
| hssi_ctr_u_ial_top_rnr_ialup_flp_inst_iapctl_comclk |
iapctl_comclk_false |
| hssi_ctr_u_ial_top_rnr_ialup_flp_inst_iapctl_force_ial |
iapctl_force_ial_false |
| hssi_ctr_u_ial_top_rnr_ialup_flp_inst_sosctl_srisen |
sosctl_srisen_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_cxl_ldid_en |
ldid_enable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_ialpmmctl_vid |
32902 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_ialpmmctl_vmeb15 |
72 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rcrbbar_en |
rcrbbar_en_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cfg_avmm_csr_k_partial_bypass_configload |
cfg_avmm_csr_k_partial_bypass_configload_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_chemem_ctrl_k_perframe_addr_steer_opt |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_chemem_ctrl_k_perframe_cqid_steer_opt |
chemem_ctrl_k_perframe_cqid_steer_opt_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_chemem_ctrl_k_perframe_slice_en |
chemem_ctrl_k_perframe_slice_en_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_clk_csr_k_clkreq_hysterisis |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_clk_csr_k_clock_control |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_clk_csr_k_osc_clk_dis |
clk_csr_k_osc_clk_dis_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cvp_ctrl_2_k_compressed |
cvp_ctrl_2_k_compressed_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cvp_ctrl_2_k_devbrd_type |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cvp_ctrl_2_k_encryped |
cvp_ctrl_2_k_encryped_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cvp_ctrl_3_k_jtag_id_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cvp_ctrl_4_k_jtag_id_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cvp_ctrl_5_k_jtag_id_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cvp_ctrl_6_k_jtag_id_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cvp_ctrl_7_k_cvp_irq_en |
cvp_ctrl_7_k_cvp_irq_en_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cvp_ctrl_7_k_cvp_write_mask_ctl |
cvp_ctrl_7_k_cvp_write_mask_ctl_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_cvp_ctrl_7_k_gpio_irq |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_h2d_arb_ctrl_k_h2drsp_throttle_en |
h2d_arb_ctrl_k_h2drsp_throttle_en_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_ica_ctrl_k_ica_dbg_stepthrumode |
ica_ctrl_k_ica_dbg_stepthrumode_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_opcode_lock_k_opcode_lock |
opcode_lock_k_opcode_lock_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_aer_cntrl_reg_aer_ecrc_chk_capable |
pf0_aer_cntrl_reg_aer_ecrc_chk_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_aer_cntrl_reg_aer_ecrc_gen_capable |
pf0_aer_cntrl_reg_aer_ecrc_gen_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_ats_reg_global_inval_suppport |
pf0_ats_reg_global_inval_suppport_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_ats_reg_inval_queue_dep |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_ats_reg_page_aglign_req |
pf0_ats_reg_page_aglign_req_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_ats_reg_ro_support |
pf0_ats_reg_ro_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_devcapreg2_cpl_to_dis_support |
pf0_devcapreg2_cpl_to_dis_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_devcapreg2_ee_tlp_prefix_support |
pf0_devcapreg2_ee_tlp_prefix_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_devcapreg2_tph_cpl_support |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_devcapreg_ep_l0_acc_lat |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_devcapreg_ep_l1_acc_lat |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_devcapreg_flr_cap |
pf0_devcapreg_flr_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_devcapreg_rb_err_rptr |
pf0_devcapreg_rb_err_rptr_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_devvendid_deviceid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_devvendid_vendorid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range1_size_high_memory_range1_size_high |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range1_size_low_desired_interleave_range1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range1_size_low_media_type_range1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range1_size_low_memory_active_range1 |
pf0_dvsec_flex_bus_range1_size_low_memory_active_range1_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range1_size_low_memory_class_range1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range1_size_low_memory_info_valid_range1 |
pf0_dvsec_flex_bus_range1_size_low_memory_info_valid_range1_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range1_size_low_memory_range1_size_low |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range2_size_high_memory_range2_size_high |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range2_size_low_desired_interleave_range2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range2_size_low_media_type_range2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range2_size_low_memory_active_range2 |
pf0_dvsec_flex_bus_range2_size_low_memory_active_range2_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range2_size_low_memory_class_range2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range2_size_low_memory_info_valid_range2 |
pf0_dvsec_flex_bus_range2_size_low_memory_info_valid_range2_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_flex_bus_range2_size_low_memory_range2_size_low |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_head2_cap_dvsecid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_head2_cap_hdm_count |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_head2_cap_mem_hwinit_mode |
pf0_dvsec_head2_cap_mem_hwinit_mode_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_dvsec_head2_cap_viral_capable |
pf0_dvsec_head2_cap_viral_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_msi_cap_reg_extnd_msg_data_capable |
pf0_msi_cap_reg_extnd_msg_data_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_msi_cap_reg_mul_msg_cap |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_msi_cap_reg_per_vector_msk_cap |
pf0_msi_cap_reg_per_vector_msk_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_msix_cap_reg_table_sz |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_msix_pba_ptr_pba_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_msix_pba_ptr_pba_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_msix_table_ptr_table_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_msix_table_ptr_table_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_pasid_reg_exec_permi_supp |
pf0_pasid_reg_exec_permi_supp_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_pasid_reg_pasid_max_width |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_pasid_reg_privil_mode_supp |
pf0_pasid_reg_privil_mode_supp_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_ptm_cap_reg_local_clock_granularity |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_ptm_cap_reg_ptm_rqstr_capable |
pf0_ptm_cap_reg_ptm_rqstr_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_reset_entry_bypass_reset_entry_bypass_idle_check |
pf0_reset_entry_bypass_reset_entry_bypass_idle_check_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_revclasscode_class_codes |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_revclasscode_rid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_siov_dvsec_flags_h |
pf0_siov_dvsec_flags_h_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_siov_dvsec_funtion_dependency_link |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_siov_reg3_ims_support |
pf0_siov_reg3_ims_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_sriov_cap_vf_mig_cap |
pf0_sriov_cap_vf_mig_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_sriov_cap_vf_mig_int |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_subsystemid_subsystemid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_subsystemid_subsystemvendorid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_tph_req_cap_reg_dev_spec_mode_supd |
pf0_tph_req_cap_reg_dev_spec_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_tph_req_cap_reg_etph_req_supd |
pf0_tph_req_cap_reg_etph_req_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_tph_req_cap_reg_int_vct_mode_supd |
pf0_tph_req_cap_reg_int_vct_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_tph_req_cap_reg_st_table_loc |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_tph_req_cap_reg_tph_st_tab_size |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_0_vf_ats_globalinv_support_0 |
pf0_vf_atscap_0_vf_ats_globalinv_support_0_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_0_vf_ats_invqueue_depth_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_0_vf_ats_pagealignedreq_0 |
pf0_vf_atscap_0_vf_ats_pagealignedreq_0_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_1_vf_ats_globalinv_support_1 |
pf0_vf_atscap_1_vf_ats_globalinv_support_1_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_1_vf_ats_invqueue_depth_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_1_vf_ats_pagealignedreq_1 |
pf0_vf_atscap_1_vf_ats_pagealignedreq_1_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_2_vf_ats_globalinv_support_2 |
pf0_vf_atscap_2_vf_ats_globalinv_support_2_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_2_vf_ats_invqueue_depth_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_2_vf_ats_pagealignedreq_2 |
pf0_vf_atscap_2_vf_ats_pagealignedreq_2_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_3_vf_ats_globalinv_support_3 |
pf0_vf_atscap_3_vf_ats_globalinv_support_3_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_3_vf_ats_invqueue_depth_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_3_vf_ats_pagealignedreq_3 |
pf0_vf_atscap_3_vf_ats_pagealignedreq_3_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_4_vf_ats_globalinv_support_4 |
pf0_vf_atscap_4_vf_ats_globalinv_support_4_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_4_vf_ats_invqueue_depth_4 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_4_vf_ats_pagealignedreq_4 |
pf0_vf_atscap_4_vf_ats_pagealignedreq_4_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_5_vf_ats_globalinv_support_5 |
pf0_vf_atscap_5_vf_ats_globalinv_support_5_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_5_vf_ats_invqueue_depth_5 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_5_vf_ats_pagealignedreq_5 |
pf0_vf_atscap_5_vf_ats_pagealignedreq_5_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_6_vf_ats_globalinv_support_6 |
pf0_vf_atscap_6_vf_ats_globalinv_support_6_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_6_vf_ats_invqueue_depth_6 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_6_vf_ats_pagealignedreq_6 |
pf0_vf_atscap_6_vf_ats_pagealignedreq_6_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_7_vf_ats_globalinv_support_7 |
pf0_vf_atscap_7_vf_ats_globalinv_support_7_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_7_vf_ats_invqueue_depth_7 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_atscap_7_vf_ats_pagealignedreq_7 |
pf0_vf_atscap_7_vf_ats_pagealignedreq_7_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_device_id_vf_device_id |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_0_vf_msix_pba_bir_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_0_vf_msix_pba_offset_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_1_vf_msix_pba_bir_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_1_vf_msix_pba_offset_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_2_vf_msix_pba_bir_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_2_vf_msix_pba_offset_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_3_vf_msix_pba_bir_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_3_vf_msix_pba_offset_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_4_vf_msix_pba_bir_4 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_4_vf_msix_pba_offset_4 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_5_vf_msix_pba_bir_5 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_5_vf_msix_pba_offset_5 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_6_vf_msix_pba_bir_6 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_6_vf_msix_pba_offset_6 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_7_vf_msix_pba_bir_7 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_pba_7_vf_msix_pba_offset_7 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_0_vf_msix_table_bir_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_0_vf_msix_table_offset_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_1_vf_msix_table_bir_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_1_vf_msix_table_offset_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_2_vf_msix_table_bir_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_2_vf_msix_table_offset_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_3_vf_msix_table_bir_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_3_vf_msix_table_offset_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_4_vf_msix_table_bir_4 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_4_vf_msix_table_offset_4 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_5_vf_msix_table_bir_5 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_5_vf_msix_table_offset_5 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_6_vf_msix_table_bir_6 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_6_vf_msix_table_offset_6 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_7_vf_msix_table_bir_7 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_msix_table_7_vf_msix_table_offset_7 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_offset_stride_first_vf_off |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_capabilities_0_vf_msix_tablesz_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_capabilities_1_vf_msix_tablesz_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_capabilities_2_vf_msix_tablesz_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_capabilities_3_vf_msix_tablesz_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_capabilities_4_vf_msix_tablesz_4 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_capabilities_5_vf_msix_tablesz_5 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_capabilities_6_vf_msix_tablesz_6 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_capabilities_7_vf_msix_tablesz_7 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_0_vf_revision_id_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_0_vf_subysystem_id_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_1_vf_revision_id_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_1_vf_subysystem_id_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_2_vf_revision_id_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_2_vf_subysystem_id_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_3_vf_revision_id_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_3_vf_subysystem_id_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_4_vf_revision_id_4 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_4_vf_subysystem_id_4 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_5_vf_revision_id_5 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_5_vf_subysystem_id_5 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_6_vf_revision_id_6 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_6_vf_subysystem_id_6 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_7_vf_revision_id_7 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_pci_cfg_7_vf_subysystem_id_7 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_0_vf_tph_devspecific_mode_0 |
pf0_vf_tphcap_0_vf_tph_devspecific_mode_0_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_0_vf_tph_exttphreq_0 |
pf0_vf_tphcap_0_vf_tph_exttphreq_0_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_0_vf_tph_intvec_mode_0 |
pf0_vf_tphcap_0_vf_tph_intvec_mode_0_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_0_vf_tph_sttable_loc_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_0_vf_tph_sttable_size_0 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_1_vf_tph_devspecific_mode_1 |
pf0_vf_tphcap_1_vf_tph_devspecific_mode_1_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_1_vf_tph_exttphreq_1 |
pf0_vf_tphcap_1_vf_tph_exttphreq_1_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_1_vf_tph_intvec_mode_1 |
pf0_vf_tphcap_1_vf_tph_intvec_mode_1_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_1_vf_tph_sttable_loc_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_1_vf_tph_sttable_size_1 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_2_vf_tph_devspecific_mode_2 |
pf0_vf_tphcap_2_vf_tph_devspecific_mode_2_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_2_vf_tph_exttphreq_2 |
pf0_vf_tphcap_2_vf_tph_exttphreq_2_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_2_vf_tph_intvec_mode_2 |
pf0_vf_tphcap_2_vf_tph_intvec_mode_2_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_2_vf_tph_sttable_loc_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_2_vf_tph_sttable_size_2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_3_vf_tph_devspecific_mode_3 |
pf0_vf_tphcap_3_vf_tph_devspecific_mode_3_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_3_vf_tph_exttphreq_3 |
pf0_vf_tphcap_3_vf_tph_exttphreq_3_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_3_vf_tph_intvec_mode_3 |
pf0_vf_tphcap_3_vf_tph_intvec_mode_3_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_3_vf_tph_sttable_loc_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_3_vf_tph_sttable_size_3 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_4_vf_tph_devspecific_mode_4 |
pf0_vf_tphcap_4_vf_tph_devspecific_mode_4_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_4_vf_tph_exttphreq_4 |
pf0_vf_tphcap_4_vf_tph_exttphreq_4_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_4_vf_tph_intvec_mode_4 |
pf0_vf_tphcap_4_vf_tph_intvec_mode_4_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_4_vf_tph_sttable_loc_4 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_4_vf_tph_sttable_size_4 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_5_vf_tph_devspecific_mode_5 |
pf0_vf_tphcap_5_vf_tph_devspecific_mode_5_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_5_vf_tph_exttphreq_5 |
pf0_vf_tphcap_5_vf_tph_exttphreq_5_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_5_vf_tph_intvec_mode_5 |
pf0_vf_tphcap_5_vf_tph_intvec_mode_5_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_5_vf_tph_sttable_loc_5 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_5_vf_tph_sttable_size_5 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_6_vf_tph_devspecific_mode_6 |
pf0_vf_tphcap_6_vf_tph_devspecific_mode_6_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_6_vf_tph_exttphreq_6 |
pf0_vf_tphcap_6_vf_tph_exttphreq_6_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_6_vf_tph_intvec_mode_6 |
pf0_vf_tphcap_6_vf_tph_intvec_mode_6_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_6_vf_tph_sttable_loc_6 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_6_vf_tph_sttable_size_6 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_7_vf_tph_devspecific_mode_7 |
pf0_vf_tphcap_7_vf_tph_devspecific_mode_7_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_7_vf_tph_exttphreq_7 |
pf0_vf_tphcap_7_vf_tph_exttphreq_7_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_7_vf_tph_intvec_mode_7 |
pf0_vf_tphcap_7_vf_tph_intvec_mode_7_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_7_vf_tph_sttable_loc_7 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf0_vf_tphcap_7_vf_tph_sttable_size_7 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_ats_reg_global_inval_suppport |
pf1_ats_reg_global_inval_suppport_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_ats_reg_inval_queue_dep |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_ats_reg_page_aglign_req |
pf1_ats_reg_page_aglign_req_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_ats_reg_ro_support |
pf1_ats_reg_ro_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_devcapreg2_tph_cpl_support |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_devvendid_deviceid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_msi_cap_reg_extnd_msg_data_capable |
pf1_msi_cap_reg_extnd_msg_data_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_msi_cap_reg_mul_msg_cap |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_msi_cap_reg_per_vector_msk_cap |
pf1_msi_cap_reg_per_vector_msk_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_msix_cap_reg_function_mask |
pf1_msix_cap_reg_function_mask_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_msix_cap_reg_table_sz |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_msix_pba_ptr_pba_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_msix_pba_ptr_pba_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_msix_table_ptr_table_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_msix_table_ptr_table_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_revclasscode_class_codes |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_revclasscode_rid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_siov_dvsec_flags_h |
pf1_siov_dvsec_flags_h_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_siov_dvsec_funtion_dependency_link |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_siov_reg3_ims_support |
pf1_siov_reg3_ims_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_sriov_cap_vf_mig_cap |
pf1_sriov_cap_vf_mig_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_sriov_cap_vf_mig_int |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_tph_req_cap_reg_dev_spec_mode_supd |
pf1_tph_req_cap_reg_dev_spec_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_tph_req_cap_reg_etph_req_supd |
pf1_tph_req_cap_reg_etph_req_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_tph_req_cap_reg_int_vct_mode_supd |
pf1_tph_req_cap_reg_int_vct_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_tph_req_cap_reg_st_table_loc |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_tph_req_cap_reg_tph_st_tab_size |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_vf_device_id_vf_device_id |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf1_vf_offset_stride_first_vf_off |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_ats_reg_global_inval_suppport |
pf2_ats_reg_global_inval_suppport_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_ats_reg_inval_queue_dep |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_ats_reg_page_aglign_req |
pf2_ats_reg_page_aglign_req_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_ats_reg_ro_support |
pf2_ats_reg_ro_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_devcapreg2_tph_cpl_support |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_devvendid_deviceid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_msi_cap_reg_extnd_msg_data_capable |
pf2_msi_cap_reg_extnd_msg_data_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_msi_cap_reg_mul_msg_cap |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_msi_cap_reg_per_vector_msk_cap |
pf2_msi_cap_reg_per_vector_msk_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_msix_cap_reg_function_mask |
pf2_msix_cap_reg_function_mask_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_msix_cap_reg_table_sz |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_msix_pba_ptr_pba_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_msix_pba_ptr_pba_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_msix_table_ptr_table_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_msix_table_ptr_table_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_revclasscode_class_codes |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_revclasscode_rid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_siov_dvsec_flags_h |
pf2_siov_dvsec_flags_h_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_siov_dvsec_funtion_dependency_link |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_siov_reg3_ims_support |
pf2_siov_reg3_ims_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_sriov_cap_vf_mig_cap |
pf2_sriov_cap_vf_mig_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_sriov_cap_vf_mig_int |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_tph_req_cap_reg_dev_spec_mode_supd |
pf2_tph_req_cap_reg_dev_spec_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_tph_req_cap_reg_etph_req_supd |
pf2_tph_req_cap_reg_etph_req_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_tph_req_cap_reg_int_vct_mode_supd |
pf2_tph_req_cap_reg_int_vct_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_tph_req_cap_reg_st_table_loc |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_tph_req_cap_reg_tph_st_tab_size |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_vf_device_id_vf_device_id |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf2_vf_offset_stride_first_vf_off |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_ats_reg_global_inval_suppport |
pf3_ats_reg_global_inval_suppport_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_ats_reg_inval_queue_dep |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_ats_reg_page_aglign_req |
pf3_ats_reg_page_aglign_req_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_ats_reg_ro_support |
pf3_ats_reg_ro_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_devcapreg2_tph_cpl_support |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_devvendid_deviceid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_msi_cap_reg_extnd_msg_data_capable |
pf3_msi_cap_reg_extnd_msg_data_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_msi_cap_reg_mul_msg_cap |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_msi_cap_reg_per_vector_msk_cap |
pf3_msi_cap_reg_per_vector_msk_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_msix_cap_reg_function_mask |
pf3_msix_cap_reg_function_mask_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_msix_cap_reg_table_sz |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_msix_pba_ptr_pba_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_msix_pba_ptr_pba_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_msix_table_ptr_table_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_msix_table_ptr_table_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_revclasscode_class_codes |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_revclasscode_rid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_siov_dvsec_flags_h |
pf3_siov_dvsec_flags_h_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_siov_dvsec_funtion_dependency_link |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_siov_reg3_ims_support |
pf3_siov_reg3_ims_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_sriov_cap_vf_mig_cap |
pf3_sriov_cap_vf_mig_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_sriov_cap_vf_mig_int |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_tph_req_cap_reg_dev_spec_mode_supd |
pf3_tph_req_cap_reg_dev_spec_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_tph_req_cap_reg_etph_req_supd |
pf3_tph_req_cap_reg_etph_req_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_tph_req_cap_reg_int_vct_mode_supd |
pf3_tph_req_cap_reg_int_vct_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_tph_req_cap_reg_st_table_loc |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_tph_req_cap_reg_tph_st_tab_size |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_vf_device_id_vf_device_id |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf3_vf_offset_stride_first_vf_off |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_ats_reg_global_inval_suppport |
pf4_ats_reg_global_inval_suppport_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_ats_reg_inval_queue_dep |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_ats_reg_page_aglign_req |
pf4_ats_reg_page_aglign_req_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_ats_reg_ro_support |
pf4_ats_reg_ro_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_devcapreg2_tph_cpl_support |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_devvendid_deviceid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_msi_cap_reg_extnd_msg_data_capable |
pf4_msi_cap_reg_extnd_msg_data_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_msi_cap_reg_mul_msg_cap |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_msi_cap_reg_per_vector_msk_cap |
pf4_msi_cap_reg_per_vector_msk_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_msix_cap_reg_function_mask |
pf4_msix_cap_reg_function_mask_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_msix_cap_reg_table_sz |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_msix_pba_ptr_pba_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_msix_pba_ptr_pba_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_msix_table_ptr_table_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_msix_table_ptr_table_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_revclasscode_class_codes |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_revclasscode_rid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_siov_dvsec_flags_h |
pf4_siov_dvsec_flags_h_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_siov_dvsec_funtion_dependency_link |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_siov_reg3_ims_support |
pf4_siov_reg3_ims_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_sriov_cap_vf_mig_cap |
pf4_sriov_cap_vf_mig_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_sriov_cap_vf_mig_int |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_tph_req_cap_reg_dev_spec_mode_supd |
pf4_tph_req_cap_reg_dev_spec_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_tph_req_cap_reg_etph_req_supd |
pf4_tph_req_cap_reg_etph_req_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_tph_req_cap_reg_int_vct_mode_supd |
pf4_tph_req_cap_reg_int_vct_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_tph_req_cap_reg_st_table_loc |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_tph_req_cap_reg_tph_st_tab_size |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_vf_device_id_vf_device_id |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf4_vf_offset_stride_first_vf_off |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_ats_reg_global_inval_suppport |
pf5_ats_reg_global_inval_suppport_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_ats_reg_inval_queue_dep |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_ats_reg_page_aglign_req |
pf5_ats_reg_page_aglign_req_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_ats_reg_ro_support |
pf5_ats_reg_ro_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_devcapreg2_tph_cpl_support |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_devvendid_deviceid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_msi_cap_reg_extnd_msg_data_capable |
pf5_msi_cap_reg_extnd_msg_data_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_msi_cap_reg_mul_msg_cap |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_msi_cap_reg_per_vector_msk_cap |
pf5_msi_cap_reg_per_vector_msk_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_msix_cap_reg_function_mask |
pf5_msix_cap_reg_function_mask_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_msix_cap_reg_table_sz |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_msix_pba_ptr_pba_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_msix_pba_ptr_pba_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_msix_table_ptr_table_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_msix_table_ptr_table_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_revclasscode_class_codes |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_revclasscode_rid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_siov_dvsec_flags_h |
pf5_siov_dvsec_flags_h_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_siov_dvsec_funtion_dependency_link |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_siov_reg3_ims_support |
pf5_siov_reg3_ims_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_sriov_cap_vf_mig_cap |
pf5_sriov_cap_vf_mig_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_sriov_cap_vf_mig_int |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_tph_req_cap_reg_dev_spec_mode_supd |
pf5_tph_req_cap_reg_dev_spec_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_tph_req_cap_reg_etph_req_supd |
pf5_tph_req_cap_reg_etph_req_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_tph_req_cap_reg_int_vct_mode_supd |
pf5_tph_req_cap_reg_int_vct_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_tph_req_cap_reg_st_table_loc |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_tph_req_cap_reg_tph_st_tab_size |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_vf_device_id_vf_device_id |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf5_vf_offset_stride_first_vf_off |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_ats_reg_global_inval_suppport |
pf6_ats_reg_global_inval_suppport_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_ats_reg_inval_queue_dep |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_ats_reg_page_aglign_req |
pf6_ats_reg_page_aglign_req_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_ats_reg_ro_support |
pf6_ats_reg_ro_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_devcapreg2_tph_cpl_support |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_devvendid_deviceid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_msi_cap_reg_extnd_msg_data_capable |
pf6_msi_cap_reg_extnd_msg_data_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_msi_cap_reg_mul_msg_cap |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_msi_cap_reg_per_vector_msk_cap |
pf6_msi_cap_reg_per_vector_msk_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_msix_cap_reg_function_mask |
pf6_msix_cap_reg_function_mask_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_msix_cap_reg_table_sz |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_msix_pba_ptr_pba_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_msix_pba_ptr_pba_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_msix_table_ptr_table_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_msix_table_ptr_table_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_revclasscode_class_codes |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_revclasscode_rid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_siov_dvsec_flags_h |
pf6_siov_dvsec_flags_h_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_siov_dvsec_funtion_dependency_link |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_siov_reg3_ims_support |
pf6_siov_reg3_ims_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_sriov_cap_vf_mig_cap |
pf6_sriov_cap_vf_mig_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_sriov_cap_vf_mig_int |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_tph_req_cap_reg_dev_spec_mode_supd |
pf6_tph_req_cap_reg_dev_spec_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_tph_req_cap_reg_etph_req_supd |
pf6_tph_req_cap_reg_etph_req_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_tph_req_cap_reg_int_vct_mode_supd |
pf6_tph_req_cap_reg_int_vct_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_tph_req_cap_reg_st_table_loc |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_tph_req_cap_reg_tph_st_tab_size |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_vf_device_id_vf_device_id |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf6_vf_offset_stride_first_vf_off |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_ats_reg_global_inval_suppport |
pf7_ats_reg_global_inval_suppport_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_ats_reg_inval_queue_dep |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_ats_reg_page_aglign_req |
pf7_ats_reg_page_aglign_req_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_ats_reg_ro_support |
pf7_ats_reg_ro_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_devcapreg2_tph_cpl_support |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_devvendid_deviceid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_msi_cap_reg_extnd_msg_data_capable |
pf7_msi_cap_reg_extnd_msg_data_capable_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_msi_cap_reg_mul_msg_cap |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_msi_cap_reg_per_vector_msk_cap |
pf7_msi_cap_reg_per_vector_msk_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_msix_cap_reg_function_mask |
pf7_msix_cap_reg_function_mask_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_msix_cap_reg_table_sz |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_msix_pba_ptr_pba_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_msix_pba_ptr_pba_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_msix_table_ptr_table_bir |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_msix_table_ptr_table_offset |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_revclasscode_class_codes |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_revclasscode_rid |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_siov_dvsec_flags_h |
pf7_siov_dvsec_flags_h_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_siov_dvsec_funtion_dependency_link |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_siov_reg3_ims_support |
pf7_siov_reg3_ims_support_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_sriov_cap_vf_mig_cap |
pf7_sriov_cap_vf_mig_cap_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_sriov_cap_vf_mig_int |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_tph_req_cap_reg_dev_spec_mode_supd |
pf7_tph_req_cap_reg_dev_spec_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_tph_req_cap_reg_etph_req_supd |
pf7_tph_req_cap_reg_etph_req_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_tph_req_cap_reg_int_vct_mode_supd |
pf7_tph_req_cap_reg_int_vct_mode_supd_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_tph_req_cap_reg_st_table_loc |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_tph_req_cap_reg_tph_st_tab_size |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_vf_device_id_vf_device_id |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pf7_vf_offset_stride_first_vf_off |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_pld_sbep_portid_k_pld_sbep_id |
128 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_powerdown_mode |
true |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_r_spare_ctl2_k_r_spare_ctl2 |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_reset_csr_k_pld_crs_en |
reset_csr_k_pld_crs_en_false |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_sup_mode |
user_mode |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_addr_a2a3_data_pack |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_acs_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_aer_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_ats_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_cxl_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_ltr_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_msi_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_msix_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_pasid_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_pcie_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_pm_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_pri_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_ptm_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_siov_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_sriov_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_tph_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cfg_ext_vc_next_ptr |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cvp_bar_num |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_cvp_mode |
cvp_disabled |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_functional_mode |
normal |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_maxpayload_size |
max_payload_1024 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_num_of_pf |
num_1 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_aer_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_cxl_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_expansion_rom_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_expansion_rom_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_ltr_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_msi_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_num_of_vf |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_pasid_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_prs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_ptm_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_siov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_sriov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vc_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf0_vf_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_aer_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_msi_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_num_of_vf |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_pasid_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_prs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_siov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_sriov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf1_vf_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_aer_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_msi_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_num_of_vf |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_pasid_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_prs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_siov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_sriov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf2_vf_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_aer_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_msi_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_num_of_vf |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_pasid_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_prs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_siov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_sriov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf3_vf_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_aer_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_msi_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_num_of_vf |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_pasid_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_prs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_siov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_sriov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf4_vf_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_aer_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_msi_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_num_of_vf |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_pasid_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_prs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_siov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_sriov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf5_vf_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_aer_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_msi_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_num_of_vf |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_pasid_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_prs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_siov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_sriov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf6_vf_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_aer_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_msi_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_num_of_vf |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_pasid_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_prs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_siov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_sriov_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_acs_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_ats_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar0_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar0_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar0_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar0_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar1_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar1_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar1_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar2_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar2_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar2_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar2_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar3_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar3_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar3_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar4_64b_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar4_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar4_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar4_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar5_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar5_mask |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_bar5_prefetchable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_msix_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pf7_vf_tph_cap_enable |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_pri_out_pagereq_capacity |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_ptile_header_fmt |
disable |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_supported_page_size |
0 |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_rnr_pialup_inst_virtual_tag_support |
tag_5bit |
| hssi_ctr_u_ial_top_rnr_ialup_icm_inst_target_link_speed |
gen5 |
| hssi_ctr_u_ial_top_sup_mode |
user_mode |
| hssi_ctr_u_pcie_top_powerdown_mode |
false |
| hssi_ctr_u_pcie_top_ptm_enable |
disabled |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_avmm_ctrl_k_rstrdy_resp_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_avmm_ctrl_k_security_bypass_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_deskew_ctrl_k_dskw_force_done_p0_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_deskew_ctrl_k_dskw_force_done_p1_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_deskew_ctrl_k_dskw_force_done_p2_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_deskew_ctrl_k_dskw_force_done_p3_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl1_k_dfd_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl1_k_dfd_patcntr_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl1_k_xbar0_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl1_k_xbar1_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl1_k_xbar2_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl1_k_xbar3_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl2_k_lane0_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl2_k_lane1_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl2_k_lane2_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl2_k_lane3_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl3_k_trig0_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl3_k_trig1_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl_k_dfd_q0_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl_k_dfd_q1_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl_k_dfd_q2_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_dfdmux_ctrl_k_dfd_q3_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_ecc_ctrl_k_ecc_aib_sel_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_ecc_ctrl_k_ecc_error_mask_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_ecc_ctrl_k_ecc_sts_cor_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_ecc_ctrl_k_ecc_sts_uc_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_ecc_ctrl_k_nparity_ecc_attr |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_ecc_ctrl_k_par_sts_uc_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_cfgtop_inst_hw_mode_override_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ats_ctl0_k_exvf_ats_pagealignreq_pf0_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ats_ctl0_k_exvf_ats_pagealignreq_pf1_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ats_ctl0_k_exvf_ats_pagealignreq_pf2_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ats_ctl0_k_exvf_ats_pagealignreq_pf3_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ats_ctl1_k_exvf_ats_pagealignreq_pf4_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ats_ctl1_k_exvf_ats_pagealignreq_pf5_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ats_ctl1_k_exvf_ats_pagealignreq_pf6_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ats_ctl1_k_exvf_ats_pagealignreq_pf7_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_0_k_cii_addr_size0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_0_k_cii_pf_en0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_0_k_cii_start_addr0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_1_k_cii_addr_size1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_1_k_cii_pf_en1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_1_k_cii_start_addr1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_2_k_cii_addr_size2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_2_k_cii_pf_en2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_2_k_cii_start_addr2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_3_k_cii_addr_size3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_3_k_cii_pf_en3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_3_k_cii_start_addr3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_4_k_cii_addr_size4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_4_k_cii_pf_en4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_4_k_cii_start_addr4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_5_k_cii_addr_size5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_5_k_cii_pf_en5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_5_k_cii_start_addr5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_6_k_cii_addr_size6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_6_k_cii_pf_en6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_6_k_cii_start_addr6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_7_k_cii_addr_size7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_7_k_cii_pf_en7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cii_range_7_k_cii_start_addr7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_csb_ctrl0_k_cfg_sys_serr_dis_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_csb_ctrl0_k_fixedcred_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_csb_ctrl0_k_mcred_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_csb_ctrl0_k_reloadcred_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_csb_ctrl0_k_tlp_serr_dis_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_csb_mmio_access_ctrl_grant_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_csb_opcode_ctrl_lock_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_bar0_k_cvp_bar_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_bar1_k_cvp_bar_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_ctl_k_cvp_bar_mode_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_ctl_k_cvp_bar_type_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_ctl_k_cvp_bar_used_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_ctrl0_k_compressed_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_ctrl0_k_encrypted_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_ctrl1_k_devbrd_type_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_ctrl1_k_vsec_next_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_irq_ctrl_k_cvp_irq_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_irq_ctrl_k_gpio_irq_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_irq_ctrl_k_irq_misc_ctrl_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_cvp_jtagid0_k_jtag_id_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_ctrl0_k_dfd_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_ctrl0_k_patcntr_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_data_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_data_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_data_sel_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_data_sel_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_trig_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_trig_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_xbar_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_xbar_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_xbar_sel_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dfd_xbar_sel_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dwc_ctrl0_k_dbi_ro_wr_disable_attr |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dwc_ctrl0_k_pld_aib_loopback_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dwc_ctrl0_k_pld_crs_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dwc_ctrl0_k_rx_lane_flip_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dwc_ctrl0_k_sris_mode_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_dwc_ctrl0_k_tx_lane_flip_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ehp_ctrl0_k_ehp_control_reg_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ehp_ctrl1_k_outstanding_crd_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ehp_ctrl1_k_tx_rd_th_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ehp_tx_int_msg_cpl_ctrl_cpl_always_grant_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ehp_tx_int_msg_cpl_ctrl_msg_always_grant_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff0_k_exvf_msixpba_bir_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff0_k_exvf_msixpba_offset_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff1_k_exvf_msixpba_bir_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff1_k_exvf_msixpba_offset_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff2_k_exvf_msixpba_bir_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff2_k_exvf_msixpba_offset_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff3_k_exvf_msixpba_bir_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff3_k_exvf_msixpba_offset_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff4_k_exvf_msixpba_bir_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff4_k_exvf_msixpba_offset_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff5_k_exvf_msixpba_bir_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff5_k_exvf_msixpba_offset_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff6_k_exvf_msixpba_bir_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff6_k_exvf_msixpba_offset_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff7_k_exvf_msixpba_bir_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_poff7_k_exvf_msixpba_offset_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff0_k_exvf_msixtable_bir_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff0_k_exvf_msixtable_offset_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff1_k_exvf_msixtable_bir_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff1_k_exvf_msixtable_offset_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff2_k_exvf_msixtable_bir_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff2_k_exvf_msixtable_offset_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff3_k_exvf_msixtable_bir_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff3_k_exvf_msixtable_offset_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff4_k_exvf_msixtable_bir_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff4_k_exvf_msixtable_offset_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff5_k_exvf_msixtable_bir_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff5_k_exvf_msixtable_offset_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff6_k_exvf_msixtable_bir_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff6_k_exvf_msixtable_offset_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff7_k_exvf_msixtable_bir_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_toff7_k_exvf_msixtable_offset_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_tsize0_k_exvf_msix_tablesize_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_tsize0_k_exvf_msix_tablesize_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_tsize1_k_exvf_msix_tablesize_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_tsize1_k_exvf_msix_tablesize_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_tsize2_k_exvf_msix_tablesize_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_tsize2_k_exvf_msix_tablesize_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_tsize3_k_exvf_msix_tablesize_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_m6_tsize3_k_exvf_msix_tablesize_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_cfg_ram_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_cfg_ram_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_csb_msg_dropped_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_cvp_cfg_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_dbi_access_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_dwc_rx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_dwc_tx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_ehp_rx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_ehp_rx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_ehp_tx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_ehp_tx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_pipe_msgbuf_overflow_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_rcvd_pm_to_ack_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_irq_en_k_rcvd_pm_turnoff_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_cfg_ram_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_cfg_ram_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_csb_msg_dropped_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_cvp_cfg_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_dbi_access_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_dwc_rx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_dwc_tx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_ehp_rx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_ehp_rx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_ehp_tx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_ehp_tx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_pipe_msgbuf_overflow_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_rcvd_pm_to_ack_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_misc_ssm_irq_en_k_rcvd_pm_turnoff_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_acs_capabilities_ctrl_reg_acs_at_block |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_acs_capabilities_ctrl_reg_acs_src_valid |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_acs_capabilities_ctrl_reg_acs_usp_forwarding |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar0_reg_bar0_type |
pf0_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar2_reg_bar2_type |
pf0_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar3_reg_bar3_mem_io |
pf0_bar3_mem |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar4_reg_bar4_type |
pf0_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_cap_id_nxt_ptr_reg_dsi |
pf0_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_cap_reg_ari_acs_fun_grp_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_con_status_reg_no_soft_rst |
pf0_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_device_capabilities_reg_pcie_cap_flr_cap |
pf0_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_exp_rom_base_addr_reg_rom_bar_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen2_ctrl_off_auto_lane_flip_ctrl_en |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen2_ctrl_off_config_phy_tx_change |
pf0_full_swing |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen2_ctrl_off_support_mod_ts |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable |
pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable_atg4 |
gen4_pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable_atg5 |
gen5_pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode |
pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode_atg4 |
gen4_pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode_atg5 |
gen5_pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec |
2047 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec_atg4 |
927 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec_atg5 |
927 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable_atg4 |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable_atg5 |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_eq_eieos_cnt |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_eq_eieos_cnt_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_eq_eieos_cnt_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_eq_phase_2_3 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_eq_phase_2_3_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_eq_phase_2_3_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_eq_redo |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_eq_redo_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_eq_redo_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_gen3_equalization_disable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_gen3_equalization_disable_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_gen3_equalization_disable_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_rxeq_ph01_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_rxeq_ph01_en_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_rxeq_ph01_en_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts_atg4 |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts_atg5 |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1_substates_off_l1sub_t_l1_2 |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1_substates_off_l1sub_t_power_off |
2 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_capability_reg_comm_mode_support |
10 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_capability_reg_l1_1_aspm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_capability_reg_l1_1_pcipm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_capability_reg_l1_2_aspm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_capability_reg_l1_2_pcipm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_capability_reg_pwr_on_scale_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_capability_reg_pwr_on_value_support |
5 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_control1_reg_l1_1_aspm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_control1_reg_l1_1_pcipm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_control1_reg_l1_2_aspm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_control1_reg_l1_2_pcipm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_control1_reg_l1_2_th_sca |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_control1_reg_l1_2_th_val |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_l1sub_control1_reg_t_common_mode |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_link_capabilities_reg_pcie_cap_surprise_down_err_rep_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf0_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf0_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_link_control_link_status_reg_pcie_cap_link_auto_bw_int_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_link_control_link_status_reg_pcie_cap_link_bw_man_int_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf0_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_multi_lane_control_off_upconfigure_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf0_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_pcie_int_msg_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_pcie_slot_imp |
pf0_not_implemented |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pipe_loopback_control_off_pipe_loopback |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_24h_reg_dsp_16g_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_24h_reg_dsp_16g_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_24h_reg_dsp_16g_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_24h_reg_dsp_16g_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_24h_reg_usp_16g_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_24h_reg_usp_16g_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_24h_reg_usp_16g_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_24h_reg_usp_16g_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_28h_reg_dsp_16g_tx_preset10 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_28h_reg_dsp_16g_tx_preset11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_28h_reg_dsp_16g_tx_preset8 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_28h_reg_dsp_16g_tx_preset9 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_28h_reg_usp_16g_tx_preset10 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_28h_reg_usp_16g_tx_preset11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_28h_reg_usp_16g_tx_preset8 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_28h_reg_usp_16g_tx_preset9 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_2ch_reg_dsp_16g_tx_preset12 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_2ch_reg_dsp_16g_tx_preset13 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_2ch_reg_dsp_16g_tx_preset14 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_2ch_reg_dsp_16g_tx_preset15 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_2ch_reg_usp_16g_tx_preset12 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_2ch_reg_usp_16g_tx_preset13 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_2ch_reg_usp_16g_tx_preset14 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl16g_cap_off_2ch_reg_usp_16g_tx_preset15 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_24h_reg_dsp_32g_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_24h_reg_dsp_32g_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_24h_reg_dsp_32g_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_24h_reg_dsp_32g_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_24h_reg_usp_32g_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_24h_reg_usp_32g_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_24h_reg_usp_32g_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_24h_reg_usp_32g_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_28h_reg_dsp_32g_tx_preset10 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_28h_reg_dsp_32g_tx_preset11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_28h_reg_dsp_32g_tx_preset8 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_28h_reg_dsp_32g_tx_preset9 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_28h_reg_usp_32g_tx_preset10 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_28h_reg_usp_32g_tx_preset11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_28h_reg_usp_32g_tx_preset8 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_28h_reg_usp_32g_tx_preset9 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_2ch_reg_dsp_32g_tx_preset12 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_2ch_reg_dsp_32g_tx_preset13 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_2ch_reg_dsp_32g_tx_preset14 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_2ch_reg_dsp_32g_tx_preset15 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_2ch_reg_usp_32g_tx_preset12 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_2ch_reg_usp_32g_tx_preset13 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_2ch_reg_usp_32g_tx_preset14 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_cap_off_2ch_reg_usp_32g_tx_preset15 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_capability_reg_no_eq_needed_support |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_status_reg_no_eq_needed_rcvd |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_status_reg_rsvdp_11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_status_reg_rx_enh_link_behavior_ctrl |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_status_reg_tx_precode_req |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_pl32g_status_reg_tx_precoding_on |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_port_link_ctrl_off_fast_link_mode |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_root_control_root_capabilities_reg_pcie_cap_crs_sw_visibility |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_attention_indicator |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_attention_indicator_button |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_electromech_interlock |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_hot_plug_capable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_hot_plug_surprise |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_mrl_sensor |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_no_cmd_cpl_support |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_phy_slot_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_power_controller |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_power_indicator |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_slot_power_limit_scale |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_slot_capabilities_reg_pcie_cap_slot_power_limit_value |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_0ch_reg_dsp_rx_preset_hint0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_0ch_reg_dsp_rx_preset_hint1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_0ch_reg_dsp_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_0ch_reg_dsp_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_0ch_reg_usp_rx_preset_hint0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_0ch_reg_usp_rx_preset_hint1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_0ch_reg_usp_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_0ch_reg_usp_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_10h_reg_dsp_rx_preset_hint2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_10h_reg_dsp_rx_preset_hint3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_10h_reg_dsp_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_10h_reg_dsp_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_10h_reg_usp_rx_preset_hint2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_10h_reg_usp_rx_preset_hint3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_10h_reg_usp_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_10h_reg_usp_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_14h_reg_dsp_rx_preset_hint4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_14h_reg_dsp_rx_preset_hint5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_14h_reg_dsp_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_14h_reg_dsp_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_14h_reg_usp_rx_preset_hint4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_14h_reg_usp_rx_preset_hint5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_14h_reg_usp_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_14h_reg_usp_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_18h_reg_dsp_rx_preset_hint6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_18h_reg_dsp_rx_preset_hint7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_18h_reg_dsp_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_18h_reg_dsp_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_18h_reg_usp_rx_preset_hint6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_18h_reg_usp_rx_preset_hint7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_18h_reg_usp_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_18h_reg_usp_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_1ch_reg_dsp_rx_preset_hint8 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_1ch_reg_dsp_rx_preset_hint9 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_1ch_reg_dsp_tx_preset8 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_1ch_reg_dsp_tx_preset9 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_1ch_reg_usp_rx_preset_hint8 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_1ch_reg_usp_rx_preset_hint9 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_1ch_reg_usp_tx_preset8 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_1ch_reg_usp_tx_preset9 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_20h_reg_dsp_rx_preset_hint10 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_20h_reg_dsp_rx_preset_hint11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_20h_reg_dsp_tx_preset10 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_20h_reg_dsp_tx_preset11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_20h_reg_usp_rx_preset_hint10 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_20h_reg_usp_rx_preset_hint11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_20h_reg_usp_tx_preset10 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_20h_reg_usp_tx_preset11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_24h_reg_dsp_rx_preset_hint12 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_24h_reg_dsp_rx_preset_hint13 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_24h_reg_dsp_tx_preset12 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_24h_reg_dsp_tx_preset13 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_24h_reg_usp_rx_preset_hint12 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_24h_reg_usp_rx_preset_hint13 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_24h_reg_usp_tx_preset12 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_24h_reg_usp_tx_preset13 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_28h_reg_dsp_rx_preset_hint14 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_28h_reg_dsp_rx_preset_hint15 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_28h_reg_dsp_tx_preset14 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_28h_reg_dsp_tx_preset15 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_28h_reg_usp_rx_preset_hint14 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_28h_reg_usp_rx_preset_hint15 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_28h_reg_usp_tx_preset14 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_spcie_cap_off_28h_reg_usp_tx_preset15 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar0_reg_sriov_vf_bar0_type |
pf0_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar2_reg_sriov_vf_bar2_type |
pf0_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar4_reg_sriov_vf_bar4_type |
pf0_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf0_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_acs_capabilities_ctrl_reg_acs_at_block |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_acs_capabilities_ctrl_reg_acs_src_valid |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_acs_capabilities_ctrl_reg_acs_usp_forwarding |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar0_reg_bar0_type |
pf1_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar2_reg_bar2_type |
pf1_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar4_reg_bar4_type |
pf1_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_cap_id_nxt_ptr_reg_dsi |
pf1_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_con_status_reg_no_soft_rst |
pf1_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_device_capabilities_reg_pcie_cap_flr_cap |
pf1_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_exp_rom_base_addr_reg_exp_rom_base_address |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_exp_rom_base_addr_reg_rom_bar_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_link_capabilities_reg_pcie_cap_l0s_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_link_capabilities_reg_pcie_cap_l1_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf1_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf1_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf1_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf1_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf1_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar0_reg_sriov_vf_bar0_type |
pf1_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar2_reg_sriov_vf_bar2_type |
pf1_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar4_reg_sriov_vf_bar4_type |
pf1_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf1_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf1_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_acs_capabilities_ctrl_reg_acs_at_block |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_acs_capabilities_ctrl_reg_acs_src_valid |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_acs_capabilities_ctrl_reg_acs_usp_forwarding |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar0_reg_bar0_type |
pf2_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar2_reg_bar2_type |
pf2_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar4_reg_bar4_type |
pf2_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_cap_id_nxt_ptr_reg_dsi |
pf2_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_con_status_reg_no_soft_rst |
pf2_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_device_capabilities_reg_pcie_cap_flr_cap |
pf2_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_exp_rom_base_addr_reg_exp_rom_base_address |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_exp_rom_base_addr_reg_rom_bar_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_link_capabilities_reg_pcie_cap_l0s_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_link_capabilities_reg_pcie_cap_l1_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf2_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf2_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf2_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf2_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf2_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar0_reg_sriov_vf_bar0_type |
pf2_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar2_reg_sriov_vf_bar2_type |
pf2_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar4_reg_sriov_vf_bar4_type |
pf2_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf2_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf2_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_acs_capabilities_ctrl_reg_acs_at_block |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_acs_capabilities_ctrl_reg_acs_src_valid |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_acs_capabilities_ctrl_reg_acs_usp_forwarding |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar0_reg_bar0_type |
pf3_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar2_reg_bar2_type |
pf3_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar4_reg_bar4_type |
pf3_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_cap_id_nxt_ptr_reg_dsi |
pf3_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_con_status_reg_no_soft_rst |
pf3_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_device_capabilities_reg_pcie_cap_flr_cap |
pf3_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_exp_rom_base_addr_reg_exp_rom_base_address |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_exp_rom_base_addr_reg_rom_bar_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_link_capabilities_reg_pcie_cap_l0s_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_link_capabilities_reg_pcie_cap_l1_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf3_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf3_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf3_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf3_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf3_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar0_reg_sriov_vf_bar0_type |
pf3_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar2_reg_sriov_vf_bar2_type |
pf3_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar4_reg_sriov_vf_bar4_type |
pf3_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf3_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf3_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_acs_capabilities_ctrl_reg_acs_at_block |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_acs_capabilities_ctrl_reg_acs_src_valid |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_acs_capabilities_ctrl_reg_acs_usp_forwarding |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar0_reg_bar0_type |
pf4_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar2_reg_bar2_type |
pf4_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar4_reg_bar4_type |
pf4_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_cap_id_nxt_ptr_reg_dsi |
pf4_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_con_status_reg_no_soft_rst |
pf4_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_device_capabilities_reg_pcie_cap_flr_cap |
pf4_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_exp_rom_base_addr_reg_exp_rom_base_address |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_exp_rom_base_addr_reg_rom_bar_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_link_capabilities_reg_pcie_cap_l0s_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_link_capabilities_reg_pcie_cap_l1_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf4_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf4_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf4_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf4_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf4_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar0_reg_sriov_vf_bar0_type |
pf4_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar2_reg_sriov_vf_bar2_type |
pf4_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar4_reg_sriov_vf_bar4_type |
pf4_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf4_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf4_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_acs_capabilities_ctrl_reg_acs_at_block |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_acs_capabilities_ctrl_reg_acs_src_valid |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_acs_capabilities_ctrl_reg_acs_usp_forwarding |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar0_reg_bar0_type |
pf5_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar2_reg_bar2_type |
pf5_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar4_reg_bar4_type |
pf5_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_cap_id_nxt_ptr_reg_dsi |
pf5_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_con_status_reg_no_soft_rst |
pf5_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_device_capabilities_reg_pcie_cap_flr_cap |
pf5_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_exp_rom_base_addr_reg_exp_rom_base_address |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_exp_rom_base_addr_reg_rom_bar_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_link_capabilities_reg_pcie_cap_l0s_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_link_capabilities_reg_pcie_cap_l1_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf5_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf5_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf5_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf5_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf5_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar0_reg_sriov_vf_bar0_type |
pf5_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar2_reg_sriov_vf_bar2_type |
pf5_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar4_reg_sriov_vf_bar4_type |
pf5_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf5_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf5_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_acs_capabilities_ctrl_reg_acs_at_block |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_acs_capabilities_ctrl_reg_acs_src_valid |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_acs_capabilities_ctrl_reg_acs_usp_forwarding |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar0_reg_bar0_type |
pf6_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar2_reg_bar2_type |
pf6_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar4_reg_bar4_type |
pf6_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_cap_id_nxt_ptr_reg_dsi |
pf6_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_con_status_reg_no_soft_rst |
pf6_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_device_capabilities_reg_pcie_cap_flr_cap |
pf6_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_exp_rom_base_addr_reg_exp_rom_base_address |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_exp_rom_base_addr_reg_rom_bar_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_link_capabilities_reg_pcie_cap_l0s_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_link_capabilities_reg_pcie_cap_l1_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf6_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf6_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf6_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf6_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf6_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar0_reg_sriov_vf_bar0_type |
pf6_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar2_reg_sriov_vf_bar2_type |
pf6_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar4_reg_sriov_vf_bar4_type |
pf6_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf6_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf6_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_acs_capabilities_ctrl_reg_acs_at_block |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_acs_capabilities_ctrl_reg_acs_src_valid |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_acs_capabilities_ctrl_reg_acs_usp_forwarding |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar0_reg_bar0_type |
pf7_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar2_reg_bar2_type |
pf7_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar4_reg_bar4_type |
pf7_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_cap_id_nxt_ptr_reg_dsi |
pf7_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_con_status_reg_no_soft_rst |
pf7_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_device_capabilities_reg_pcie_cap_flr_cap |
pf7_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_exp_rom_base_addr_reg_exp_rom_base_address |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_exp_rom_base_addr_reg_rom_bar_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_link_capabilities_reg_pcie_cap_l0s_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_link_capabilities_reg_pcie_cap_l1_exit_latency |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf7_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf7_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf7_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf7_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf7_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar0_reg_sriov_vf_bar0_type |
pf7_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar2_reg_sriov_vf_bar2_type |
pf7_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar4_reg_sriov_vf_bar4_type |
pf7_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf7_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pf7_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_pfvf_sel_vsec_enable_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_phy_rxelecidle_k_rxelecidle_disable_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_phy_rxtermination_k_rxtermination_attr |
127 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ptm_adj_lsb_k_cfg_ptm_local_clock_adj_lsb_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ptm_adj_msb_k_cfg_ptm_local_clock_adj_msb_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_ptm_ctrl_k_cfg_ptm_auto_update_signal_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_reset_ctrl0_k_cvp_intf_reset_ctl_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_reset_ctrl1_k_clrhip_not_rst_sticky_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_err_en_correct_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_err_en_fatal_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_err_en_nonfatal_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_cfg_aer_rc_err_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_cfg_bw_mgt_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_cfg_link_auto_bw_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_cfg_link_eq_req_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_cfg_pme_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_hp_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_hp_pme_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_inta_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_intb_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_intc_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_rp_irq_en_intd_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_sriov_misc_ctrl_k_nonsriov_mode_attr |
255 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_stagger_control_k_stag_dlycnt_attr |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_stagger_control_k_stag_mode_attr |
5 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_subs_id0_k_exvf_subsysid_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_subs_id0_k_exvf_subsysid_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_subs_id1_k_exvf_subsysid_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_subs_id1_k_exvf_subsysid_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_subs_id2_k_exvf_subsysid_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_subs_id2_k_exvf_subsysid_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_subs_id3_k_exvf_subsysid_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_subs_id3_k_exvf_subsysid_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_bad_dllp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_bad_tlp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_corrected_internal_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_dl_protocol_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_ecrc_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_fc_protocol_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_mlf_tlp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_rcvr_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_rcvr_overflow_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_replay_number_rollover_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_replay_timer_timeout_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_surprise_down_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tlb_err_en_k_cfg_uncor_internal_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl0_k_exvf_tph_sttablelocation_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl0_k_exvf_tph_sttablelocation_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl0_k_exvf_tph_sttablesize_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl0_k_exvf_tph_sttablesize_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl1_k_exvf_tph_sttablelocation_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl1_k_exvf_tph_sttablelocation_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl1_k_exvf_tph_sttablesize_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl1_k_exvf_tph_sttablesize_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl2_k_exvf_tph_sttablelocation_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl2_k_exvf_tph_sttablelocation_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl2_k_exvf_tph_sttablesize_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl2_k_exvf_tph_sttablesize_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl3_k_exvf_tph_sttablelocation_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl3_k_exvf_tph_sttablelocation_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl3_k_exvf_tph_sttablesize_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tph_ctl3_k_exvf_tph_sttablesize_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_tx_common_mode_k_txcommonmode_disable_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_100_k_pf4_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_102_k_pf4_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_103_k_pf4_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_104_k_pf4_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_106_k_pf4_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_107_k_pf4_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_108_k_pf4_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_109_k_pf4_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_10_k_pf0_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_111_k_pf5_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_112_k_pf5_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_113_k_pf5_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_115_k_pf5_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_116_k_pf5_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_117_k_pf5_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_118_k_pf5_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_11_k_pf0_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_120_k_pf5_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_121_k_pf5_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_122_k_pf5_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_124_k_pf5_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_125_k_pf5_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_126_k_pf5_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_128_k_pf5_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_129_k_pf5_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_12_k_pf0_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_130_k_pf5_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_131_k_pf5_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_133_k_pf6_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_134_k_pf6_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_135_k_pf6_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_137_k_pf6_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_138_k_pf6_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_139_k_pf6_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_140_k_pf6_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_142_k_pf6_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_143_k_pf6_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_144_k_pf6_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_146_k_pf6_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_147_k_pf6_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_148_k_pf6_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_14_k_pf0_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_150_k_pf6_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_151_k_pf6_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_152_k_pf6_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_153_k_pf6_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_155_k_pf7_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_156_k_pf7_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_157_k_pf7_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_159_k_pf7_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_15_k_pf0_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_160_k_pf7_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_161_k_pf7_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_162_k_pf7_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_164_k_pf7_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_165_k_pf7_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_166_k_pf7_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_168_k_pf7_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_169_k_pf7_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_16_k_pf0_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_170_k_pf7_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_172_k_pf7_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_173_k_pf7_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_174_k_pf7_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_175_k_pf7_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_18_k_pf0_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_19_k_pf0_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_1_k_pf0_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_20_k_pf0_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_21_k_pf0_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_23_k_pf1_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_24_k_pf1_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_25_k_pf1_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_27_k_pf1_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_28_k_pf1_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_29_k_pf1_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_2_k_pf0_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_30_k_pf1_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_32_k_pf1_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_33_k_pf1_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_34_k_pf1_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_36_k_pf1_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_37_k_pf1_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_38_k_pf1_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_3_k_pf0_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_40_k_pf1_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_41_k_pf1_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_42_k_pf1_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_43_k_pf1_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_45_k_pf2_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_46_k_pf2_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_47_k_pf2_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_49_k_pf2_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_50_k_pf2_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_51_k_pf2_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_52_k_pf2_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_54_k_pf2_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_55_k_pf2_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_56_k_pf2_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_58_k_pf2_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_59_k_pf2_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_5_k_pf0_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_60_k_pf2_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_62_k_pf2_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_63_k_pf2_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_64_k_pf2_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_65_k_pf2_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_67_k_pf3_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_68_k_pf3_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_69_k_pf3_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_6_k_pf0_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_71_k_pf3_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_72_k_pf3_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_73_k_pf3_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_74_k_pf3_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_76_k_pf3_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_77_k_pf3_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_78_k_pf3_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_7_k_pf0_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_80_k_pf3_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_81_k_pf3_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_82_k_pf3_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_84_k_pf3_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_85_k_pf3_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_86_k_pf3_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_87_k_pf3_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_89_k_pf4_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_8_k_pf0_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_90_k_pf4_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_91_k_pf4_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_93_k_pf4_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_94_k_pf4_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_95_k_pf4_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_96_k_pf4_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_98_k_pf4_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_99_k_pf4_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_cii_ctrl_k_cfg_update_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_cii_ctrl_k_cii_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtio_cii_ctrl_k_pfdata_vf_virtio_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_cvp_mode |
cvp_disabled |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_drop_vendor0_msg |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_drop_vendor1_msg |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_ep_native |
native |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_maxpayload_size |
max_payload_128 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_num_of_lanes |
num_16 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_dlink_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_io_decode |
io32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_l1_1sub_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_l1_2sub_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_ltr_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_prefetch_decode |
pref64 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_virtio_en |
pf0_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf0_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_virtio_en |
pf1_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf1_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_virtio_en |
pf2_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf2_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_virtio_en |
pf3_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf3_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_virtio_en |
pf4_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf4_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_virtio_en |
pf5_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf5_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_virtio_en |
pf6_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf6_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_virtio_en |
pf7_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_pf7_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_ptm_autoupdate |
autoupdate_10ms |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p0_inst_rnr_pcie_ip16_inst_virtual_tlp_bypass_en_dwc_ctrl0_k_ecrc_strip_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_0_k_cii_addr_size0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_0_k_cii_pf_en0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_0_k_cii_start_addr0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_1_k_cii_addr_size1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_1_k_cii_pf_en1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_1_k_cii_start_addr1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_2_k_cii_addr_size2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_2_k_cii_pf_en2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_2_k_cii_start_addr2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_3_k_cii_addr_size3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_3_k_cii_pf_en3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_3_k_cii_start_addr3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_4_k_cii_addr_size4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_4_k_cii_pf_en4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_4_k_cii_start_addr4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_5_k_cii_addr_size5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_5_k_cii_pf_en5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_5_k_cii_start_addr5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_6_k_cii_addr_size6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_6_k_cii_pf_en6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_6_k_cii_start_addr6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_7_k_cii_addr_size7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_7_k_cii_pf_en7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cii_range_7_k_cii_start_addr7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_csb_ctrl0_k_cfg_sys_serr_dis_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_csb_ctrl0_k_fixedcred_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_csb_ctrl0_k_mcred_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_csb_ctrl0_k_reloadcred_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_csb_ctrl0_k_tlp_serr_dis_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_csb_mmio_access_ctrl_grant_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_csb_opcode_ctrl_lock_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_ctrl0_k_compressed_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_ctrl0_k_encrypted_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_ctrl1_k_devbrd_type_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_ctrl1_k_vsec_next_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_irq_ctrl_k_cvp_irq_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_irq_ctrl_k_gpio_irq_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_irq_ctrl_k_irq_misc_ctrl_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_jtagid0_k_jtag_id_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_jtagid1_k_jtag_id_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_jtagid2_k_jtag_id_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_cvp_jtagid3_k_jtag_id_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_ctrl0_k_dfd_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_ctrl0_k_patcntr_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_data_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_data_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_data_sel_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_data_sel_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_trig_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_trig_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_xbar_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_xbar_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_xbar_sel_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dfd_xbar_sel_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_dbi_ro_wr_disable_attr |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_pld_aib_loopback_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_pld_crs_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_rx_lane_flip_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_sris_mode_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_tx_lane_flip_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_ehp_ctrl0_k_ehp_control_reg_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_ehp_ctrl1_k_outstanding_crd_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_ehp_ctrl1_k_tx_rd_th_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_ehp_tx_int_msg_cpl_ctrl_cpl_always_grant_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_ehp_tx_int_msg_cpl_ctrl_msg_always_grant_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_cfg_ram_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_cfg_ram_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_csb_msg_dropped_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_cvp_cfg_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_dbi_access_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_dwc_rx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_dwc_tx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_ehp_rx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_ehp_rx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_ehp_tx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_ehp_tx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_pipe_msgbuf_overflow_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_rcvd_pm_to_ack_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_irq_en_k_rcvd_pm_turnoff_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_cfg_ram_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_cfg_ram_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_csb_msg_dropped_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_cvp_cfg_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_dbi_access_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_dwc_rx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_dwc_tx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_ehp_rx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_ehp_rx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_ehp_tx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_ehp_tx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_pipe_msgbuf_overflow_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_rcvd_pm_to_ack_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_rcvd_pm_turnoff_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_at_block |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_src_valid |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_usp_forwarding |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar0_reg_bar0_type |
pf0_bar0_mem64 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar2_reg_bar2_type |
pf0_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar3_reg_bar3_mem_io |
pf0_bar3_mem |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar4_reg_bar4_type |
pf0_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_bist_header_type_latency_cache_line_size_reg_multi_func |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_cap_id_nxt_ptr_reg_dsi |
pf0_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_cap_reg_ari_acs_fun_grp_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_con_status_reg_no_soft_rst |
pf0_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_device_capabilities_reg_pcie_cap_ext_tag_supp |
pf0_supported |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_device_capabilities_reg_pcie_cap_flr_cap |
pf0_not_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_exp_rom_base_addr_reg_rom_bar_enable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen2_ctrl_off_auto_lane_flip_ctrl_en |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen2_ctrl_off_config_phy_tx_change |
pf0_full_swing |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen2_ctrl_off_select_deemph_var_mux |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen2_ctrl_off_selectable_deemph_bit_mux |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen2_ctrl_off_support_mod_ts |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable |
pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable_atg4 |
gen4_pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable_atg5 |
gen5_pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode |
pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode_atg4 |
gen4_pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode_atg5 |
gen5_pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec |
2047 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec_atg4 |
927 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec_atg5 |
927 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable_atg4 |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable_atg5 |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_eieos_cnt |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_eieos_cnt_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_eieos_cnt_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_phase_2_3 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_phase_2_3_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_phase_2_3_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_redo |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_redo_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_redo_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_gen3_equalization_disable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_gen3_equalization_disable_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_gen3_equalization_disable_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_ph01_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_ph01_en_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_ph01_en_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts_atg4 |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts_atg5 |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1_substates_off_l1sub_t_l1_2 |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1_substates_off_l1sub_t_power_off |
2 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_comm_mode_support |
10 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_l1_1_aspm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_l1_1_pcipm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_l1_2_aspm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_l1_2_pcipm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_pwr_on_scale_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_pwr_on_value_support |
5 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_1_aspm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_1_pcipm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_2_aspm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_2_pcipm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_2_th_sca |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_2_th_val |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_t_common_mode |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_link_capabilities_reg_pcie_cap_surprise_down_err_rep_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf0_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf0_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_link_control_link_status_reg_pcie_cap_link_auto_bw_int_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_link_control_link_status_reg_pcie_cap_link_bw_man_int_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf0_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_misc_control_1_off_port_logic_wr_disable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_multi_lane_control_off_upconfigure_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf0_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_pcie_int_msg_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_pcie_slot_imp |
pf0_not_implemented |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pipe_loopback_control_off_pipe_loopback |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_capability_reg_no_eq_needed_support |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_status_reg_no_eq_needed_rcvd |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_status_reg_rsvdp_11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_status_reg_rx_enh_link_behavior_ctrl |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_status_reg_tx_precode_req |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_pl32g_status_reg_tx_precoding_on |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_port_force_off_support_part_lanes_rxei_exit |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_port_link_ctrl_off_fast_link_mode |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_root_control_root_capabilities_reg_pcie_cap_crs_sw_visibility |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_attention_indicator |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_attention_indicator_button |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_electromech_interlock |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_hot_plug_capable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_hot_plug_surprise |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_mrl_sensor |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_no_cmd_cpl_support |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_phy_slot_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_power_controller |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_power_indicator |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_slot_power_limit_scale |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_slot_power_limit_value |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_dsp_rx_preset_hint0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_dsp_rx_preset_hint1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_dsp_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_dsp_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_usp_rx_preset_hint0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_usp_rx_preset_hint1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_usp_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_usp_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_dsp_rx_preset_hint2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_dsp_rx_preset_hint3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_dsp_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_dsp_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_usp_rx_preset_hint2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_usp_rx_preset_hint3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_usp_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_usp_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pf0_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_pfvf_sel_vsec_enable_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_phy_rxelecidle_k_rxelecidle_disable_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_phy_rxtermination_k_rxtermination_attr |
127 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_reset_ctrl1_k_clrhip_not_rst_sticky_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_err_en_correct_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_err_en_fatal_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_err_en_nonfatal_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_cfg_aer_rc_err_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_cfg_bw_mgt_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_cfg_link_auto_bw_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_cfg_link_eq_req_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_cfg_pme_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_hp_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_hp_pme_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_inta_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_intb_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_intc_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_rp_irq_en_intd_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_stagger_control_k_stag_dlycnt_attr |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_stagger_control_k_stag_mode_attr |
5 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_bad_dllp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_bad_tlp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_corrected_internal_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_dl_protocol_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_ecrc_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_fc_protocol_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_mlf_tlp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_rcvr_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_rcvr_overflow_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_replay_number_rollover_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_replay_timer_timeout_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_surprise_down_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_uncor_internal_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_bad_dllp_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_bad_tlp_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_corrected_internal_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_dl_protocol_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_ecrc_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_fc_protocol_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_mlf_tlp_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_rcvr_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_rcvr_overflow_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_replay_number_rollover_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_replay_timer_timeout_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_surprise_down_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_uncor_internal_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_tx_common_mode_k_txcommonmode_disable_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_10_k_pf0_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_11_k_pf0_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_12_k_pf0_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_14_k_pf0_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_15_k_pf0_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_16_k_pf0_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_18_k_pf0_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_19_k_pf0_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_1_k_pf0_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_20_k_pf0_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_21_k_pf0_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_2_k_pf0_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_3_k_pf0_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_5_k_pf0_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_6_k_pf0_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_7_k_pf0_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_8_k_pf0_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_cii_ctrl_k_cfg_update_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_cii_ctrl_k_cii_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtio_cii_ctrl_k_pfdata_vf_virtio_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_cvp_mode |
cvp_disabled |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_drop_vendor0_msg |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_drop_vendor1_msg |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_ep_native |
native |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_maxpayload_size |
max_payload_128 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_num_of_lanes |
num_4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_dlink_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_io_decode |
io32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_l1_1sub_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_l1_2sub_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_ltr_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_prefetch_decode |
pref64 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_virtio_en |
pf0_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_pf0_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_ptm_autoupdate |
autoupdate_10ms |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip4_inst_virtual_tlp_bypass_en_dwc_ctrl0_k_ecrc_strip_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ats_ctl0_k_exvf_ats_pagealignreq_pf0_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ats_ctl0_k_exvf_ats_pagealignreq_pf1_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ats_ctl0_k_exvf_ats_pagealignreq_pf2_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ats_ctl0_k_exvf_ats_pagealignreq_pf3_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ats_ctl1_k_exvf_ats_pagealignreq_pf4_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ats_ctl1_k_exvf_ats_pagealignreq_pf5_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ats_ctl1_k_exvf_ats_pagealignreq_pf6_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ats_ctl1_k_exvf_ats_pagealignreq_pf7_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_0_k_cii_addr_size0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_0_k_cii_pf_en0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_0_k_cii_start_addr0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_1_k_cii_addr_size1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_1_k_cii_pf_en1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_1_k_cii_start_addr1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_2_k_cii_addr_size2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_2_k_cii_pf_en2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_2_k_cii_start_addr2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_3_k_cii_addr_size3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_3_k_cii_pf_en3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_3_k_cii_start_addr3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_4_k_cii_addr_size4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_4_k_cii_pf_en4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_4_k_cii_start_addr4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_5_k_cii_addr_size5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_5_k_cii_pf_en5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_5_k_cii_start_addr5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_6_k_cii_addr_size6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_6_k_cii_pf_en6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_6_k_cii_start_addr6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_7_k_cii_addr_size7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_7_k_cii_pf_en7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cii_range_7_k_cii_start_addr7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_csb_ctrl0_k_cfg_sys_serr_dis_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_csb_ctrl0_k_fixedcred_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_csb_ctrl0_k_mcred_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_csb_ctrl0_k_reloadcred_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_csb_ctrl0_k_tlp_serr_dis_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_csb_mmio_access_ctrl_grant_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_csb_opcode_ctrl_lock_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_ctrl0_k_compressed_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_ctrl0_k_encrypted_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_ctrl1_k_devbrd_type_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_ctrl1_k_vsec_next_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_irq_ctrl_k_cvp_irq_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_irq_ctrl_k_gpio_irq_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_irq_ctrl_k_irq_misc_ctrl_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_jtagid0_k_jtag_id_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_jtagid1_k_jtag_id_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_jtagid2_k_jtag_id_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_cvp_jtagid3_k_jtag_id_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_ctrl0_k_dfd_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_ctrl0_k_patcntr_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_data_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_data_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_data_sel_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_data_sel_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_trig_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_trig_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_xbar_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_xbar_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_xbar_sel_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dfd_xbar_sel_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dwc_ctrl0_k_dbi_ro_wr_disable_attr |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dwc_ctrl0_k_pld_aib_loopback_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dwc_ctrl0_k_pld_crs_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dwc_ctrl0_k_rx_lane_flip_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dwc_ctrl0_k_sris_mode_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_dwc_ctrl0_k_tx_lane_flip_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ehp_ctrl0_k_ehp_control_reg_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ehp_ctrl1_k_outstanding_crd_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ehp_ctrl1_k_tx_rd_th_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ehp_tx_int_msg_cpl_ctrl_cpl_always_grant_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ehp_tx_int_msg_cpl_ctrl_msg_always_grant_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff0_k_exvf_msixpba_bir_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff0_k_exvf_msixpba_offset_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff1_k_exvf_msixpba_bir_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff1_k_exvf_msixpba_offset_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff2_k_exvf_msixpba_bir_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff2_k_exvf_msixpba_offset_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff3_k_exvf_msixpba_bir_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff3_k_exvf_msixpba_offset_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff4_k_exvf_msixpba_bir_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff4_k_exvf_msixpba_offset_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff5_k_exvf_msixpba_bir_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff5_k_exvf_msixpba_offset_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff6_k_exvf_msixpba_bir_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff6_k_exvf_msixpba_offset_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff7_k_exvf_msixpba_bir_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_poff7_k_exvf_msixpba_offset_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff0_k_exvf_msixtable_bir_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff0_k_exvf_msixtable_offset_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff1_k_exvf_msixtable_bir_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff1_k_exvf_msixtable_offset_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff2_k_exvf_msixtable_bir_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff2_k_exvf_msixtable_offset_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff3_k_exvf_msixtable_bir_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff3_k_exvf_msixtable_offset_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff4_k_exvf_msixtable_bir_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff4_k_exvf_msixtable_offset_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff5_k_exvf_msixtable_bir_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff5_k_exvf_msixtable_offset_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff6_k_exvf_msixtable_bir_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff6_k_exvf_msixtable_offset_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff7_k_exvf_msixtable_bir_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_toff7_k_exvf_msixtable_offset_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_tsize0_k_exvf_msix_tablesize_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_tsize0_k_exvf_msix_tablesize_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_tsize1_k_exvf_msix_tablesize_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_tsize1_k_exvf_msix_tablesize_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_tsize2_k_exvf_msix_tablesize_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_tsize2_k_exvf_msix_tablesize_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_tsize3_k_exvf_msix_tablesize_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_m6_tsize3_k_exvf_msix_tablesize_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_cfg_ram_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_cfg_ram_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_csb_msg_dropped_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_cvp_cfg_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_dbi_access_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_dwc_rx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_dwc_tx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_ehp_rx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_ehp_rx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_ehp_tx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_ehp_tx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_pipe_msgbuf_overflow_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_rcvd_pm_to_ack_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_irq_en_k_rcvd_pm_turnoff_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_cfg_ram_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_cfg_ram_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_csb_msg_dropped_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_cvp_cfg_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_dbi_access_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_dwc_rx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_dwc_tx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_ehp_rx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_ehp_rx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_ehp_tx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_ehp_tx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_pipe_msgbuf_overflow_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_rcvd_pm_to_ack_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_misc_ssm_irq_en_k_rcvd_pm_turnoff_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_acs_capabilities_ctrl_reg_acs_at_block |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_acs_capabilities_ctrl_reg_acs_src_valid |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_acs_capabilities_ctrl_reg_acs_usp_forwarding |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar0_reg_bar0_type |
pf0_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar2_reg_bar2_type |
pf0_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar3_reg_bar3_mem_io |
pf0_bar3_mem |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar4_reg_bar4_type |
pf0_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_cap_id_nxt_ptr_reg_dsi |
pf0_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_cap_reg_ari_acs_fun_grp_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_con_status_reg_no_soft_rst |
pf0_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_device_capabilities_reg_pcie_cap_ext_tag_supp |
pf0_not_supported |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_device_capabilities_reg_pcie_cap_flr_cap |
pf0_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_exp_rom_base_addr_reg_rom_bar_enable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen2_ctrl_off_auto_lane_flip_ctrl_en |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen2_ctrl_off_config_phy_tx_change |
pf0_full_swing |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen2_ctrl_off_select_deemph_var_mux |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen2_ctrl_off_selectable_deemph_bit_mux |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen2_ctrl_off_support_mod_ts |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable |
pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable_atg4 |
gen4_pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable_atg5 |
gen5_pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode |
pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode_atg4 |
gen4_pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode_atg5 |
gen5_pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec |
2047 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec_atg4 |
927 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec_atg5 |
927 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable_atg4 |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable_atg5 |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_eq_eieos_cnt |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_eq_eieos_cnt_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_eq_eieos_cnt_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_eq_phase_2_3 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_eq_phase_2_3_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_eq_phase_2_3_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_eq_redo |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_eq_redo_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_eq_redo_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_gen3_equalization_disable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_gen3_equalization_disable_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_gen3_equalization_disable_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_rxeq_ph01_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_rxeq_ph01_en_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_rxeq_ph01_en_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts_atg4 |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts_atg5 |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1_substates_off_l1sub_t_l1_2 |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1_substates_off_l1sub_t_power_off |
2 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_capability_reg_comm_mode_support |
10 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_capability_reg_l1_1_aspm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_capability_reg_l1_1_pcipm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_capability_reg_l1_2_aspm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_capability_reg_l1_2_pcipm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_capability_reg_pwr_on_scale_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_capability_reg_pwr_on_value_support |
5 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_control1_reg_l1_1_aspm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_control1_reg_l1_1_pcipm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_control1_reg_l1_2_aspm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_control1_reg_l1_2_pcipm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_control1_reg_l1_2_th_sca |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_control1_reg_l1_2_th_val |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_l1sub_control1_reg_t_common_mode |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_link_capabilities_reg_pcie_cap_surprise_down_err_rep_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf0_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf0_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_link_control_link_status_reg_pcie_cap_link_auto_bw_int_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_link_control_link_status_reg_pcie_cap_link_bw_man_int_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf0_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_multi_lane_control_off_upconfigure_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf0_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_pcie_int_msg_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_pcie_slot_imp |
pf0_not_implemented |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pipe_loopback_control_off_pipe_loopback |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_24h_reg_dsp_16g_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_24h_reg_dsp_16g_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_24h_reg_dsp_16g_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_24h_reg_dsp_16g_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_24h_reg_usp_16g_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_24h_reg_usp_16g_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_24h_reg_usp_16g_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl16g_cap_off_24h_reg_usp_16g_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_24h_reg_dsp_32g_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_24h_reg_dsp_32g_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_24h_reg_dsp_32g_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_24h_reg_dsp_32g_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_24h_reg_usp_32g_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_24h_reg_usp_32g_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_24h_reg_usp_32g_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_cap_off_24h_reg_usp_32g_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_capability_reg_no_eq_needed_support |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_status_reg_no_eq_needed_rcvd |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_status_reg_rsvdp_11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_status_reg_rx_enh_link_behavior_ctrl |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_status_reg_tx_precode_req |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_pl32g_status_reg_tx_precoding_on |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_port_force_off_support_part_lanes_rxei_exit |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_port_link_ctrl_off_fast_link_mode |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_root_control_root_capabilities_reg_pcie_cap_crs_sw_visibility |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_attention_indicator |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_attention_indicator_button |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_electromech_interlock |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_hot_plug_capable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_hot_plug_surprise |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_mrl_sensor |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_no_cmd_cpl_support |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_phy_slot_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_power_controller |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_power_indicator |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_slot_power_limit_scale |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_slot_capabilities_reg_pcie_cap_slot_power_limit_value |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_0ch_reg_dsp_rx_preset_hint0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_0ch_reg_dsp_rx_preset_hint1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_0ch_reg_dsp_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_0ch_reg_dsp_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_0ch_reg_usp_rx_preset_hint0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_0ch_reg_usp_rx_preset_hint1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_0ch_reg_usp_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_0ch_reg_usp_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_10h_reg_dsp_rx_preset_hint2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_10h_reg_dsp_rx_preset_hint3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_10h_reg_dsp_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_10h_reg_dsp_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_10h_reg_usp_rx_preset_hint2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_10h_reg_usp_rx_preset_hint3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_10h_reg_usp_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_10h_reg_usp_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_14h_reg_dsp_rx_preset_hint4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_14h_reg_dsp_rx_preset_hint5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_14h_reg_dsp_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_14h_reg_dsp_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_14h_reg_usp_rx_preset_hint4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_14h_reg_usp_rx_preset_hint5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_14h_reg_usp_tx_preset4 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_14h_reg_usp_tx_preset5 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_18h_reg_dsp_rx_preset_hint6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_18h_reg_dsp_rx_preset_hint7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_18h_reg_dsp_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_18h_reg_dsp_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_18h_reg_usp_rx_preset_hint6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_18h_reg_usp_rx_preset_hint7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_18h_reg_usp_tx_preset6 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_spcie_cap_off_18h_reg_usp_tx_preset7 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar0_reg_sriov_vf_bar0_type |
pf0_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar2_reg_sriov_vf_bar2_type |
pf0_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar4_reg_sriov_vf_bar4_type |
pf0_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_int_vec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_tph_req_cap_reg_reg_tph_req_device_spec |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf0_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_acs_capabilities_ctrl_reg_acs_at_block |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_acs_capabilities_ctrl_reg_acs_src_valid |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_acs_capabilities_ctrl_reg_acs_usp_forwarding |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar0_reg_bar0_type |
pf1_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar2_reg_bar2_type |
pf1_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar4_reg_bar4_type |
pf1_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_cap_id_nxt_ptr_reg_dsi |
pf1_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_con_status_reg_no_soft_rst |
pf1_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_device_capabilities_reg_pcie_cap_ext_tag_supp |
pf1_supported |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_device_capabilities_reg_pcie_cap_flr_cap |
pf1_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_exp_rom_base_addr_reg_rom_bar_enable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf1_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf1_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf1_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf1_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf1_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar0_reg_sriov_vf_bar0_type |
pf1_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar2_reg_sriov_vf_bar2_type |
pf1_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar4_reg_sriov_vf_bar4_type |
pf1_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf1_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf1_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_acs_capabilities_ctrl_reg_acs_at_block |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_acs_capabilities_ctrl_reg_acs_src_valid |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_acs_capabilities_ctrl_reg_acs_usp_forwarding |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar0_reg_bar0_type |
pf2_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar2_reg_bar2_type |
pf2_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar4_reg_bar4_type |
pf2_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_cap_id_nxt_ptr_reg_dsi |
pf2_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_con_status_reg_no_soft_rst |
pf2_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_device_capabilities_reg_pcie_cap_ext_tag_supp |
pf2_supported |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_device_capabilities_reg_pcie_cap_flr_cap |
pf2_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_exp_rom_base_addr_reg_rom_bar_enable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf2_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf2_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf2_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf2_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf2_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar0_reg_sriov_vf_bar0_type |
pf2_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar2_reg_sriov_vf_bar2_type |
pf2_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar4_reg_sriov_vf_bar4_type |
pf2_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf2_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf2_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_acs_capabilities_ctrl_reg_acs_at_block |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_acs_capabilities_ctrl_reg_acs_src_valid |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_acs_capabilities_ctrl_reg_acs_usp_forwarding |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar0_reg_bar0_type |
pf3_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar2_reg_bar2_type |
pf3_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar4_reg_bar4_type |
pf3_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_cap_id_nxt_ptr_reg_dsi |
pf3_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_con_status_reg_no_soft_rst |
pf3_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_device_capabilities_reg_pcie_cap_ext_tag_supp |
pf3_supported |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_device_capabilities_reg_pcie_cap_flr_cap |
pf3_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_exp_rom_base_addr_reg_rom_bar_enable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf3_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf3_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf3_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf3_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf3_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar0_reg_sriov_vf_bar0_type |
pf3_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar2_reg_sriov_vf_bar2_type |
pf3_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar4_reg_sriov_vf_bar4_type |
pf3_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf3_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf3_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_acs_capabilities_ctrl_reg_acs_at_block |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_acs_capabilities_ctrl_reg_acs_src_valid |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_acs_capabilities_ctrl_reg_acs_usp_forwarding |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar0_reg_bar0_type |
pf4_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar2_reg_bar2_type |
pf4_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar4_reg_bar4_type |
pf4_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_cap_id_nxt_ptr_reg_dsi |
pf4_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_con_status_reg_no_soft_rst |
pf4_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_device_capabilities_reg_pcie_cap_ext_tag_supp |
pf4_supported |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_device_capabilities_reg_pcie_cap_flr_cap |
pf4_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_exp_rom_base_addr_reg_rom_bar_enable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf4_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf4_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf4_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf4_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf4_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar0_reg_sriov_vf_bar0_type |
pf4_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar2_reg_sriov_vf_bar2_type |
pf4_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar4_reg_sriov_vf_bar4_type |
pf4_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf4_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf4_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_acs_capabilities_ctrl_reg_acs_at_block |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_acs_capabilities_ctrl_reg_acs_src_valid |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_acs_capabilities_ctrl_reg_acs_usp_forwarding |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar0_reg_bar0_type |
pf5_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar2_reg_bar2_type |
pf5_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar4_reg_bar4_type |
pf5_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_cap_id_nxt_ptr_reg_dsi |
pf5_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_con_status_reg_no_soft_rst |
pf5_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_device_capabilities_reg_pcie_cap_ext_tag_supp |
pf5_supported |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_device_capabilities_reg_pcie_cap_flr_cap |
pf5_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_exp_rom_base_addr_reg_rom_bar_enable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf5_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf5_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf5_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf5_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf5_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar0_reg_sriov_vf_bar0_type |
pf5_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar2_reg_sriov_vf_bar2_type |
pf5_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar4_reg_sriov_vf_bar4_type |
pf5_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf5_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf5_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_acs_capabilities_ctrl_reg_acs_at_block |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_acs_capabilities_ctrl_reg_acs_src_valid |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_acs_capabilities_ctrl_reg_acs_usp_forwarding |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar0_reg_bar0_type |
pf6_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar2_reg_bar2_type |
pf6_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar4_reg_bar4_type |
pf6_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_cap_id_nxt_ptr_reg_dsi |
pf6_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_con_status_reg_no_soft_rst |
pf6_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_device_capabilities_reg_pcie_cap_ext_tag_supp |
pf6_supported |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_device_capabilities_reg_pcie_cap_flr_cap |
pf6_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_exp_rom_base_addr_reg_rom_bar_enable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf6_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf6_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf6_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf6_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf6_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar0_reg_sriov_vf_bar0_type |
pf6_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar2_reg_sriov_vf_bar2_type |
pf6_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar4_reg_sriov_vf_bar4_type |
pf6_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf6_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf6_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_acs_capabilities_ctrl_reg_acs_at_block |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_acs_capabilities_ctrl_reg_acs_src_valid |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_acs_capabilities_ctrl_reg_acs_usp_forwarding |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar0_reg_bar0_type |
pf7_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar2_reg_bar2_type |
pf7_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar4_reg_bar4_type |
pf7_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_cap_id_nxt_ptr_reg_dsi |
pf7_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_cardbus_cis_ptr_reg_cardbus_cis_pointer |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_con_status_reg_no_soft_rst |
pf7_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_device_capabilities_reg_pcie_cap_ext_tag_supp |
pf7_supported |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_device_capabilities_reg_pcie_cap_flr_cap |
pf7_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_exp_rom_base_addr_reg_rom_bar_enable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf7_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf7_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf7_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf7_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_shadow_sriov_vf_offset_position_shadow_sriov_vf_offset |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_shadow_sriov_vf_offset_position_shadow_sriov_vf_stride |
256 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf7_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar0_mask_reg_pci_sriov_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar0_reg_sriov_vf_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar0_reg_sriov_vf_bar0_type |
pf7_sriov_vf_bar0_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar1_mask_reg_pci_sriov_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar1_reg_sriov_vf_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar2_mask_reg_pci_sriov_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar2_reg_sriov_vf_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar2_reg_sriov_vf_bar2_type |
pf7_sriov_vf_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar3_mask_reg_pci_sriov_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar3_reg_sriov_vf_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar4_mask_reg_pci_sriov_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar4_reg_sriov_vf_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar4_reg_sriov_vf_bar4_type |
pf7_sriov_vf_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar5_mask_reg_pci_sriov_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_bar5_reg_sriov_vf_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_vf_offset_position_sriov_vf_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sriov_vf_offset_position_sriov_vf_stride |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_sup_page_sizes_reg_sriov_sup_page_size |
1363 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf7_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pf7_vf_device_id_reg_sriov_vf_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_pfvf_sel_vsec_enable_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_phy_rxelecidle_k_rxelecidle_disable_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_phy_rxtermination_k_rxtermination_attr |
127 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ptm_adj_lsb_k_cfg_ptm_local_clock_adj_lsb_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ptm_adj_msb_k_cfg_ptm_local_clock_adj_msb_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_ptm_ctrl_k_cfg_ptm_auto_update_signal_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_reset_ctrl1_k_clrhip_not_rst_sticky_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_err_en_correct_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_err_en_fatal_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_err_en_nonfatal_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_cfg_aer_rc_err_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_cfg_bw_mgt_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_cfg_link_auto_bw_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_cfg_link_eq_req_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_cfg_pme_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_hp_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_hp_pme_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_inta_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_intb_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_intc_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_rp_irq_en_intd_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_sriov_misc_ctrl_k_nonsriov_mode_attr |
255 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_stagger_control_k_stag_dlycnt_attr |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_stagger_control_k_stag_mode_attr |
5 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_subs_id0_k_exvf_subsysid_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_subs_id0_k_exvf_subsysid_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_subs_id1_k_exvf_subsysid_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_subs_id1_k_exvf_subsysid_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_subs_id2_k_exvf_subsysid_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_subs_id2_k_exvf_subsysid_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_subs_id3_k_exvf_subsysid_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_subs_id3_k_exvf_subsysid_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_bad_dllp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_bad_tlp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_corrected_internal_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_dl_protocol_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_ecrc_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_fc_protocol_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_mlf_tlp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_rcvr_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_rcvr_overflow_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_replay_number_rollover_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_replay_timer_timeout_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_surprise_down_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tlb_err_en_k_cfg_uncor_internal_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl0_k_exvf_tph_sttablelocation_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl0_k_exvf_tph_sttablelocation_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl0_k_exvf_tph_sttablesize_pf0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl0_k_exvf_tph_sttablesize_pf1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl1_k_exvf_tph_sttablelocation_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl1_k_exvf_tph_sttablelocation_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl1_k_exvf_tph_sttablesize_pf2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl1_k_exvf_tph_sttablesize_pf3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl2_k_exvf_tph_sttablelocation_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl2_k_exvf_tph_sttablelocation_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl2_k_exvf_tph_sttablesize_pf4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl2_k_exvf_tph_sttablesize_pf5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl3_k_exvf_tph_sttablelocation_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl3_k_exvf_tph_sttablelocation_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl3_k_exvf_tph_sttablesize_pf6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tph_ctl3_k_exvf_tph_sttablesize_pf7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_tx_common_mode_k_txcommonmode_disable_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_100_k_pf4_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_102_k_pf4_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_103_k_pf4_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_104_k_pf4_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_106_k_pf4_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_107_k_pf4_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_108_k_pf4_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_109_k_pf4_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_10_k_pf0_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_111_k_pf5_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_112_k_pf5_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_113_k_pf5_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_115_k_pf5_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_116_k_pf5_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_117_k_pf5_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_118_k_pf5_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_11_k_pf0_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_120_k_pf5_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_121_k_pf5_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_122_k_pf5_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_124_k_pf5_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_125_k_pf5_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_126_k_pf5_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_128_k_pf5_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_129_k_pf5_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_12_k_pf0_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_130_k_pf5_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_131_k_pf5_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_133_k_pf6_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_134_k_pf6_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_135_k_pf6_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_137_k_pf6_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_138_k_pf6_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_139_k_pf6_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_140_k_pf6_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_142_k_pf6_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_143_k_pf6_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_144_k_pf6_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_146_k_pf6_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_147_k_pf6_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_148_k_pf6_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_14_k_pf0_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_150_k_pf6_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_151_k_pf6_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_152_k_pf6_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_153_k_pf6_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_155_k_pf7_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_156_k_pf7_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_157_k_pf7_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_159_k_pf7_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_15_k_pf0_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_160_k_pf7_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_161_k_pf7_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_162_k_pf7_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_164_k_pf7_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_165_k_pf7_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_166_k_pf7_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_168_k_pf7_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_169_k_pf7_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_16_k_pf0_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_170_k_pf7_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_172_k_pf7_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_173_k_pf7_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_174_k_pf7_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_175_k_pf7_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_18_k_pf0_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_19_k_pf0_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_1_k_pf0_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_20_k_pf0_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_21_k_pf0_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_23_k_pf1_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_24_k_pf1_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_25_k_pf1_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_27_k_pf1_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_28_k_pf1_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_29_k_pf1_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_2_k_pf0_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_30_k_pf1_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_32_k_pf1_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_33_k_pf1_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_34_k_pf1_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_36_k_pf1_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_37_k_pf1_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_38_k_pf1_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_3_k_pf0_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_40_k_pf1_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_41_k_pf1_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_42_k_pf1_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_43_k_pf1_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_45_k_pf2_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_46_k_pf2_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_47_k_pf2_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_49_k_pf2_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_50_k_pf2_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_51_k_pf2_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_52_k_pf2_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_54_k_pf2_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_55_k_pf2_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_56_k_pf2_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_58_k_pf2_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_59_k_pf2_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_5_k_pf0_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_60_k_pf2_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_62_k_pf2_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_63_k_pf2_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_64_k_pf2_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_65_k_pf2_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_67_k_pf3_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_68_k_pf3_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_69_k_pf3_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_6_k_pf0_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_71_k_pf3_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_72_k_pf3_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_73_k_pf3_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_74_k_pf3_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_76_k_pf3_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_77_k_pf3_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_78_k_pf3_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_7_k_pf0_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_80_k_pf3_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_81_k_pf3_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_82_k_pf3_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_84_k_pf3_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_85_k_pf3_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_86_k_pf3_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_87_k_pf3_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_89_k_pf4_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_8_k_pf0_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_90_k_pf4_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_91_k_pf4_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_93_k_pf4_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_94_k_pf4_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_95_k_pf4_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_96_k_pf4_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_98_k_pf4_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_99_k_pf4_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_cii_ctrl_k_cfg_update_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_cii_ctrl_k_cii_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtio_cii_ctrl_k_pfdata_vf_virtio_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_cvp_mode |
cvp_disabled |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_drop_vendor0_msg |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_drop_vendor1_msg |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_ep_native |
native |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_maxpayload_size |
max_payload_128 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_num_of_lanes |
num_8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_dlink_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_io_decode |
io32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_l1_1sub_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_l1_2sub_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_ltr_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_prefetch_decode |
pref64 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_virtio_en |
pf0_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf0_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_virtio_en |
pf1_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf1_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_virtio_en |
pf2_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf2_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_virtio_en |
pf3_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf3_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_virtio_en |
pf4_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf4_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_virtio_en |
pf5_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf5_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_virtio_en |
pf6_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf6_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_exvf_virtio_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_sriov_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_sriov_num_vf_non_ari |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_sriov_vf_bar0_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_sriov_vf_bar1_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_sriov_vf_bar2_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_sriov_vf_bar3_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_sriov_vf_bar4_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_sriov_vf_bar5_enabled |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_user_vsec_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_virtio_en |
pf7_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_pf7_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_ptm_autoupdate |
autoupdate_10ms |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p1p3_inst_rnr_pcie_ip8_inst_virtual_tlp_bypass_en_dwc_ctrl0_k_ecrc_strip_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_0_k_cii_addr_size0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_0_k_cii_pf_en0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_0_k_cii_start_addr0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_1_k_cii_addr_size1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_1_k_cii_pf_en1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_1_k_cii_start_addr1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_2_k_cii_addr_size2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_2_k_cii_pf_en2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_2_k_cii_start_addr2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_3_k_cii_addr_size3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_3_k_cii_pf_en3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_3_k_cii_start_addr3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_4_k_cii_addr_size4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_4_k_cii_pf_en4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_4_k_cii_start_addr4_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_5_k_cii_addr_size5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_5_k_cii_pf_en5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_5_k_cii_start_addr5_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_6_k_cii_addr_size6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_6_k_cii_pf_en6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_6_k_cii_start_addr6_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_7_k_cii_addr_size7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_7_k_cii_pf_en7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cii_range_7_k_cii_start_addr7_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_csb_ctrl0_k_cfg_sys_serr_dis_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_csb_ctrl0_k_fixedcred_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_csb_ctrl0_k_mcred_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_csb_ctrl0_k_reloadcred_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_csb_ctrl0_k_tlp_serr_dis_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_csb_mmio_access_ctrl_grant_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_csb_opcode_ctrl_lock_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_ctrl0_k_compressed_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_ctrl0_k_encrypted_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_ctrl1_k_devbrd_type_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_ctrl1_k_vsec_next_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_irq_ctrl_k_cvp_irq_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_irq_ctrl_k_gpio_irq_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_irq_ctrl_k_irq_misc_ctrl_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_jtagid0_k_jtag_id_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_jtagid1_k_jtag_id_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_jtagid2_k_jtag_id_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_cvp_jtagid3_k_jtag_id_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_ctrl0_k_dfd_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_ctrl0_k_patcntr_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_data_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_data_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_data_sel_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_data_sel_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_trig_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_trig_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_xbar_sel_0_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_xbar_sel_1_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_xbar_sel_2_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dfd_xbar_sel_3_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_dbi_ro_wr_disable_attr |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_pld_aib_loopback_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_pld_crs_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_rx_lane_flip_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_sris_mode_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_dwc_ctrl0_k_tx_lane_flip_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_ehp_ctrl0_k_ehp_control_reg_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_ehp_ctrl1_k_outstanding_crd_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_ehp_ctrl1_k_tx_rd_th_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_ehp_tx_int_msg_cpl_ctrl_cpl_always_grant_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_ehp_tx_int_msg_cpl_ctrl_msg_always_grant_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_cfg_ram_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_cfg_ram_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_csb_msg_dropped_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_cvp_cfg_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_dbi_access_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_dwc_rx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_dwc_tx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_ehp_rx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_ehp_rx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_ehp_tx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_ehp_tx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_pipe_msgbuf_overflow_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_rcvd_pm_to_ack_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_irq_en_k_rcvd_pm_turnoff_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_cfg_ram_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_cfg_ram_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_csb_msg_dropped_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_cvp_cfg_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_dbi_access_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_dwc_rx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_dwc_tx_parity_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_ehp_rx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_ehp_rx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_ehp_tx_correctable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_ehp_tx_uncorrectable_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_pipe_msgbuf_overflow_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_rcvd_pm_to_ack_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_misc_ssm_irq_en_k_rcvd_pm_turnoff_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_at_block |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_direct_translated_p2p |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_egress_ctrl_size |
8 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_cpl_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_egress_control |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_p2p_req_redirect |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_src_valid |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_acs_capabilities_ctrl_reg_acs_usp_forwarding |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_ats_capabilities_ctrl_reg_invalidate_q_depth |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_ats_capabilities_ctrl_reg_page_aligned_req |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar0_mask_reg_pci_type0_bar0_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar0_mask_reg_pci_type0_bar0_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar0_reg_bar0_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar0_reg_bar0_type |
pf0_bar0_mem64 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar1_mask_reg_pci_type0_bar1_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar1_mask_reg_pci_type0_bar1_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar1_reg_bar1_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar2_mask_reg_pci_type0_bar2_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar2_mask_reg_pci_type0_bar2_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar2_reg_bar2_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar2_reg_bar2_type |
pf0_bar2_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar3_mask_reg_pci_type0_bar3_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar3_mask_reg_pci_type0_bar3_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar3_reg_bar3_mem_io |
pf0_bar3_mem |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar3_reg_bar3_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar4_mask_reg_pci_type0_bar4_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar4_mask_reg_pci_type0_bar4_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar4_reg_bar4_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar4_reg_bar4_type |
pf0_bar4_mem32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar5_mask_reg_pci_type0_bar5_enabled |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar5_mask_reg_pci_type0_bar5_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bar5_reg_bar5_prefetch |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_bist_header_type_latency_cache_line_size_reg_multi_func |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_cap_id_nxt_ptr_reg_aux_curr |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_cap_id_nxt_ptr_reg_dsi |
pf0_not_required |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_cap_id_nxt_ptr_reg_pme_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_cap_reg_ari_acs_fun_grp_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_class_code_revision_id_base_class_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_class_code_revision_id_program_interface |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_class_code_revision_id_revision_id |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_class_code_revision_id_subclass_code |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_con_status_reg_no_soft_rst |
pf0_not_internally_reset |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_dev3_ext_cap_device_control3_reg_dev3_cap_dmwr_egress_blk |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_device_capabilities_reg_pcie_cap_ep_l0s_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_device_capabilities_reg_pcie_cap_ep_l1_accpt_latency |
7 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_device_capabilities_reg_pcie_cap_ext_tag_supp |
pf0_supported |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_device_capabilities_reg_pcie_cap_flr_cap |
pf0_not_capable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_device_control_device_status_pcie_cap_ext_tag_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_device_id_vendor_id_reg_pci_type0_device_id |
4466 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_device_id_vendor_id_reg_pci_type0_vendor_id |
32902 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_exp_rom_bar_mask_reg_rom_bar_enabled |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_exp_rom_bar_mask_reg_rom_mask |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_exp_rom_base_addr_reg_rom_bar_enable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen2_ctrl_off_auto_lane_flip_ctrl_en |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen2_ctrl_off_config_phy_tx_change |
pf0_full_swing |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen2_ctrl_off_select_deemph_var_mux |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen2_ctrl_off_selectable_deemph_bit_mux |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen2_ctrl_off_support_mod_ts |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable |
pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable_atg4 |
gen4_pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_eval_2ms_disable_atg5 |
gen5_pf0_continue |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode |
pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode_atg4 |
gen4_pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_phase23_exit_mode_atg5 |
gen5_pf0_next_rec_equal |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec |
2047 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec_atg4 |
927 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_eq_pset_req_vec_atg5 |
927 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable_atg4 |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_eq_control_off_gen3_lower_rate_eq_redo_enable_atg5 |
enable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_eieos_cnt |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_eieos_cnt_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_eieos_cnt_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_phase_2_3 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_phase_2_3_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_phase_2_3_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_redo |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_redo_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_eq_redo_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_gen3_equalization_disable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_gen3_equalization_disable_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_gen3_equalization_disable_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_ph01_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_ph01_en_atg4 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_ph01_en_atg5 |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts_atg4 |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_gen3_related_off_rxeq_rgrdless_rxts_atg5 |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1_substates_off_l1sub_t_l1_2 |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1_substates_off_l1sub_t_power_off |
2 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_comm_mode_support |
10 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_l1_1_aspm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_l1_1_pcipm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_l1_2_aspm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_l1_2_pcipm_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_pwr_on_scale_support |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_capability_reg_pwr_on_value_support |
5 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_1_aspm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_1_pcipm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_2_aspm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_2_pcipm_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_2_th_sca |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_l1_2_th_val |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_l1sub_control1_reg_t_common_mode |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_link_capabilities_reg_pcie_cap_l0s_exit_latency |
3 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_link_capabilities_reg_pcie_cap_l1_exit_latency |
4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_link_capabilities_reg_pcie_cap_port_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_link_capabilities_reg_pcie_cap_surprise_down_err_rep_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_link_control2_link_status2_reg_pcie_cap_sel_deemphasis |
pf0_minus_6db |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_link_control_link_status_reg_pcie_cap_active_state_link_pm_control |
pf0_aspm_dis |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_link_control_link_status_reg_pcie_cap_link_auto_bw_int_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_link_control_link_status_reg_pcie_cap_link_bw_man_int_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_link_control_link_status_reg_pcie_cap_slot_clk_config |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_max_latency_min_grant_interrupt_pin_interrupt_line_reg_int_pin |
pf0_inta |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_misc_control_1_off_port_logic_wr_disable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_msix_pba_offset_reg_pci_msix_pba_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_msix_pba_offset_reg_pci_msix_pba_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_msix_table_offset_reg_pci_msix_bir |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_msix_table_offset_reg_pci_msix_table_offset |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_multi_lane_control_off_upconfigure_support |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pasid_cap_cntrl_reg_execute_permission_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pasid_cap_cntrl_reg_max_pasid_width |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pasid_cap_cntrl_reg_privileged_mode_supported |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_64_bit_addr_cap |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_cap |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_ext_data_en |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pci_msi_cap_id_next_ctrl_reg_pci_msi_multiple_msg_cap |
pf0_msi_vec_1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_pcie_int_msg_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_pcie_slot_imp |
pf0_not_implemented |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pipe_loopback_control_off_pipe_loopback |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_dsp_16g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl16g_cap_off_20h_reg_usp_16g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_dsp_32g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_cap_off_20h_reg_usp_32g_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_capability_reg_no_eq_needed_support |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_status_reg_no_eq_needed_rcvd |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_status_reg_rsvdp_11 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_status_reg_rx_enh_link_behavior_ctrl |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_status_reg_tx_precode_req |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_pl32g_status_reg_tx_precoding_on |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_port_force_off_support_part_lanes_rxei_exit |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_port_link_ctrl_off_fast_link_mode |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_prs_req_capacity_reg_prs_outstanding_capacity |
1 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_root_control_root_capabilities_reg_pcie_cap_crs_sw_visibility |
true |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_sd_eq_control1_reg_eval_interval_time |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_ser_num_reg_dw_1_sn_ser_num_reg_1_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_ser_num_reg_dw_2_sn_ser_num_reg_2_dw |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_shadow_pci_msix_cap_id_next_ctrl_reg_pci_msix_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table_vf |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_shadow_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_attention_indicator |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_attention_indicator_button |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_electromech_interlock |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_hot_plug_capable |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_hot_plug_surprise |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_mrl_sensor |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_no_cmd_cpl_support |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_phy_slot_num |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_power_controller |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_power_indicator |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_slot_power_limit_scale |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_slot_capabilities_reg_pcie_cap_slot_power_limit_value |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_dsp_rx_preset_hint0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_dsp_rx_preset_hint1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_dsp_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_dsp_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_usp_rx_preset_hint0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_usp_rx_preset_hint1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_usp_tx_preset0 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_0ch_reg_usp_tx_preset1 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_dsp_rx_preset_hint2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_dsp_rx_preset_hint3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_dsp_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_dsp_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_usp_rx_preset_hint2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_usp_rx_preset_hint3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_usp_tx_preset2 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_spcie_cap_off_10h_reg_usp_tx_preset3 |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_subsystem_id_subsystem_vendor_id_reg_subsys_dev_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_subsystem_id_subsystem_vendor_id_reg_subsys_vendor_id |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_int_vec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_tph_req_cap_reg_reg_tph_req_cap_st_table_size |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pf0_tph_req_cap_reg_reg_tph_req_device_spec |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_pfvf_sel_vsec_enable_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_phy_rxelecidle_k_rxelecidle_disable_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_phy_rxtermination_k_rxtermination_attr |
127 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_reset_ctrl1_k_clrhip_not_rst_sticky_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_err_en_correct_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_err_en_fatal_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_err_en_nonfatal_err_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_cfg_aer_rc_err_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_cfg_bw_mgt_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_cfg_link_auto_bw_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_cfg_link_eq_req_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_cfg_pme_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_hp_int_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_hp_pme_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_inta_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_intb_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_intc_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_rp_irq_en_intd_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_stagger_control_k_stag_dlycnt_attr |
6 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_stagger_control_k_stag_mode_attr |
5 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_bad_dllp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_bad_tlp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_corrected_internal_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_dl_protocol_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_ecrc_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_fc_protocol_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_mlf_tlp_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_rcvr_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_rcvr_overflow_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_replay_number_rollover_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_replay_timer_timeout_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_surprise_down_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_en_k_cfg_uncor_internal_err_sts_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_bad_dllp_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_bad_tlp_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_corrected_internal_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_dl_protocol_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_ecrc_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_fc_protocol_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_mlf_tlp_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_rcvr_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_rcvr_overflow_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_replay_number_rollover_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_replay_timer_timeout_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_surprise_down_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tlb_err_sts_cfg_uncor_internal_err_sts_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_tx_common_mode_k_txcommonmode_disable_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_10_k_pf0_virtio_offset_cfg3_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_11_k_pf0_virtio_offset_cfg3_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_12_k_pf0_virtio_offset_cfg3_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_14_k_pf0_virtio_offset_cfg4_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_15_k_pf0_virtio_offset_cfg4_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_16_k_pf0_virtio_offset_cfg4_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_18_k_pf0_virtio_offset_cfg5_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_19_k_pf0_virtio_offset_cfg5_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_1_k_pf0_virtio_offset_cfg1_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_20_k_pf0_virtio_offset_cfg5_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_21_k_pf0_virtio_offset_cfg5_cfg_data_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_2_k_pf0_virtio_offset_cfg1_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_3_k_pf0_virtio_offset_cfg1_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_5_k_pf0_virtio_offset_cfg2_cap_bar_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_6_k_pf0_virtio_offset_cfg2_cap_offset_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_7_k_pf0_virtio_offset_cfg2_cap_length_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_8_k_pf0_virtio_offset_cfg2_notify_off_multiplier_attr |
0 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_cii_ctrl_k_cfg_update_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_cii_ctrl_k_cii_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtio_cii_ctrl_k_pfdata_vf_virtio_en_attr |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_cvp_mode |
cvp_disabled |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_drop_vendor0_msg |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_drop_vendor1_msg |
false |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_ep_native |
native |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_maxpayload_size |
max_payload_128 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_num_of_lanes |
num_4 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_dlink_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_exvf_acs_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_exvf_ats_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_exvf_msix_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_exvf_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_io_decode |
io32 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_l1_1sub_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_l1_2sub_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_ltr_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_msi_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_msix_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_pasid_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_prefetch_decode |
pref64 |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_prs_ext_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_ras_des_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_sn_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_tph_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_user_vsec_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_virtio_dev_specific_conf_en |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_virtio_en |
pf0_virtio_disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_pf0_vsecras_cap_enable |
disable |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_ptm_autoupdate |
autoupdate_10ms |
| hssi_ctr_u_pcie_top_rnr_pcie_par_p2_inst_rnr_pcie_ip4_inst_virtual_tlp_bypass_en_dwc_ctrl0_k_ecrc_strip_attr |
false |
| hssi_ctr_u_pcie_top_sim_mode |
disable |
| hssi_ctr_u_pcie_top_sup_mode |
user_mode |
| hssi_ctr_u_pcie_top_virtual_dmwr_support |
false |
| hssi_ctr_u_pcie_top_virtual_l1sub_support |
false |
| hssi_ctr_u_phy_top_pcie_capable_octet0 |
octet0_gen5_capable |
| hssi_ctr_u_phy_top_pcie_capable_octet1 |
octet1_gen5_capable |
| hssi_ctr_u_phy_top_u_phy_octet0_powerdown_mode |
true |
| hssi_ctr_u_phy_top_u_phy_octet1_powerdown_mode |
true |
| hssi_ctr_u_rnr_aibaux_top_wrp_powerdown_mode |
true |
| hssi_ctr_silicon_rev |
10nm6arnra |
| select_design_example_hwtcl |
PIO using MCDMA Bypass mode |
| bar2_address_width_hwtcl |
20 |
| mode_hwtcl |
MCDMA |
| uport_type_hwtcl |
AVMM |
| num_ports_hwtcl |
1 |
| pf0_num_dma_chan_pf_hwtcl |
1 |
| enable_32bit_pio_hwtcl |
1 |
| enable_user_msix_hwtcl |
1 |
| enable_user_flr_hwtcl |
0 |
| d2h_num_active_channel_hwtcl |
8 |
| d2h_max_num_desc_fetch_hwtcl |
16 |
| en_metadata_8_hwtcl |
0 |
| enable_user_hip_reconfig_sel_hwtcl |
0 |
| enable_byte_aligned_txfr_hwtcl |
0 |
| enable_user_cii_hwtcl |
0 |
| mc_pf0_bar0_type_user_hwtcl |
64-bit prefetchable memory |
| mc_pf0_bar0_address_width_user_hwtcl |
16 |
| mc_pf0_bar1_type_user_hwtcl |
Disabled |
| mc_pf0_bar2_type_user_hwtcl |
Disabled |
| mc_pf0_bar3_type_user_hwtcl |
Disabled |
| mc_pf0_bar4_type_user_hwtcl |
Disabled |
| mc_pf0_bar5_type_user_hwtcl |
Disabled |
| mc_pf0_expansion_base_address_register_hwtcl |
0 |
| mc_pf4_expansion_base_address_register_hwtcl |
0 |
| mc_pf5_expansion_base_address_register_hwtcl |
0 |
| mc_pf6_expansion_base_address_register_hwtcl |
0 |
| mc_pf7_expansion_base_address_register_hwtcl |
0 |
| m1_mode_hwtcl |
BAM |
| m1_pf0_num_dma_chan_pf_hwtcl |
4 |
| m1_enable_32bit_address_hwtcl |
0 |
| m1_enable_user_msix_hwtcl |
0 |
| m1_enable_user_flr_hwtcl |
0 |
| m1_enable_user_hip_reconfig_sel_hwtcl |
0 |
| m1_enable_user_cii_hwtcl |
0 |
| m1_mc_pf0_bar0_type_user_hwtcl |
64-bit prefetchable memory |
| m1_mc_pf0_bar0_address_width_user_hwtcl |
16 |
| m1_mc_pf0_bar1_type_user_hwtcl |
Disabled |
| m1_mc_pf0_bar2_type_user_hwtcl |
Disabled |
| m1_mc_pf0_bar3_type_user_hwtcl |
Disabled |
| m1_mc_pf0_bar4_type_user_hwtcl |
Disabled |
| m1_mc_pf0_bar5_type_user_hwtcl |
Disabled |
| m1_mc_pf0_expansion_base_address_register_hwtcl |
0 |
| m1_mc_pf4_expansion_base_address_register_hwtcl |
0 |
| m1_mc_pf5_expansion_base_address_register_hwtcl |
0 |
| m1_mc_pf6_expansion_base_address_register_hwtcl |
0 |
| m1_mc_pf7_expansion_base_address_register_hwtcl |
0 |
| m1_dm_virtual_pf0_msix_enable_user_hwtcl |
0 |
| m1_dm_virtual_pf1_msix_enable_user_hwtcl |
0 |
| m1_dm_virtual_pf2_msix_enable_user_hwtcl |
0 |
| m1_dm_virtual_pf3_msix_enable_user_hwtcl |
0 |
| m1_dm_virtual_pf4_msix_enable_user_hwtcl |
0 |
| m1_dm_virtual_pf5_msix_enable_user_hwtcl |
0 |
| m1_dm_virtual_pf6_msix_enable_user_hwtcl |
0 |
| m1_dm_virtual_pf7_msix_enable_user_hwtcl |
0 |
| m1_dm_pf0_pci_msix_table_size_hwtcl |
0 |
| m1_dm_pf0_pci_msix_table_offset_hwtcl |
0 |
| m1_dm_pf0_pci_msix_bir_hwtcl |
0 |
| m1_dm_pf0_pci_msix_pba_offset_hwtcl |
0 |
| m1_dm_pf0_pci_msix_pba_hwtcl |
0 |
| m1_dm_pf1_pci_msix_table_size_hwtcl |
0 |
| m1_dm_pf1_pci_msix_table_offset_hwtcl |
0 |
| m1_dm_pf1_pci_msix_bir_hwtcl |
0 |
| m1_dm_pf1_pci_msix_pba_offset_hwtcl |
0 |
| m1_dm_pf1_pci_msix_pba_hwtcl |
0 |
| m1_dm_pf2_pci_msix_table_size_hwtcl |
0 |
| m1_dm_pf2_pci_msix_table_offset_hwtcl |
0 |
| m1_dm_pf2_pci_msix_bir_hwtcl |
0 |
| m1_dm_pf2_pci_msix_pba_offset_hwtcl |
0 |
| m1_dm_pf2_pci_msix_pba_hwtcl |
0 |
| m1_dm_pf3_pci_msix_table_size_hwtcl |
0 |
| m1_dm_pf3_pci_msix_table_offset_hwtcl |
0 |
| m1_dm_pf3_pci_msix_bir_hwtcl |
0 |
| m1_dm_pf3_pci_msix_pba_offset_hwtcl |
0 |
| m1_dm_pf3_pci_msix_pba_hwtcl |
0 |
| m1_dm_pf4_pci_msix_table_size_hwtcl |
0 |
| m1_dm_pf4_pci_msix_table_offset_hwtcl |
0 |
| m1_dm_pf4_pci_msix_bir_hwtcl |
0 |
| m1_dm_pf4_pci_msix_pba_offset_hwtcl |
0 |
| m1_dm_pf4_pci_msix_pba_hwtcl |
0 |
| m1_dm_pf5_pci_msix_table_size_hwtcl |
0 |
| m1_dm_pf5_pci_msix_table_offset_hwtcl |
0 |
| m1_dm_pf5_pci_msix_bir_hwtcl |
0 |
| m1_dm_pf5_pci_msix_pba_offset_hwtcl |
0 |
| m1_dm_pf5_pci_msix_pba_hwtcl |
0 |
| m1_dm_pf6_pci_msix_table_size_hwtcl |
0 |
| m1_dm_pf6_pci_msix_table_offset_hwtcl |
0 |
| m1_dm_pf6_pci_msix_bir_hwtcl |
0 |
| m1_dm_pf6_pci_msix_pba_offset_hwtcl |
0 |
| m1_dm_pf6_pci_msix_pba_hwtcl |
0 |
| m1_dm_pf7_pci_msix_table_size_hwtcl |
0 |
| m1_dm_pf7_pci_msix_table_offset_hwtcl |
0 |
| m1_dm_pf7_pci_msix_bir_hwtcl |
0 |
| m1_dm_pf7_pci_msix_pba_offset_hwtcl |
0 |
| m1_dm_pf7_pci_msix_pba_hwtcl |
0 |
| m1_dm_virtual_pf0_exvf_msix_cap_enable_hwtcl |
0 |
| m1_dm_exvf_msix_tablesize_pf0 |
0 |
| m1_dm_exvf_msixtable_offset_pf0 |
0 |
| m1_dm_exvf_msixtable_bir_pf0 |
0 |
| m1_dm_exvf_msixpba_offset_pf0 |
0 |
| m1_dm_exvf_msixpba_bir_pf0 |
0 |
| m1_dm_virtual_pf1_exvf_msix_cap_enable_hwtcl |
0 |
| m1_dm_exvf_msix_tablesize_pf1 |
0 |
| m1_dm_exvf_msixtable_offset_pf1 |
0 |
| m1_dm_exvf_msixtable_bir_pf1 |
0 |
| m1_dm_exvf_msixpba_offset_pf1 |
0 |
| m1_dm_exvf_msixpba_bir_pf1 |
0 |
| m1_dm_virtual_pf2_exvf_msix_cap_enable_hwtcl |
0 |
| m1_dm_exvf_msix_tablesize_pf2 |
0 |
| m1_dm_exvf_msixtable_offset_pf2 |
0 |
| m1_dm_exvf_msixtable_bir_pf2 |
0 |
| m1_dm_exvf_msixpba_offset_pf2 |
0 |
| m1_dm_exvf_msixpba_bir_pf2 |
0 |
| m1_dm_virtual_pf3_exvf_msix_cap_enable_hwtcl |
0 |
| m1_dm_exvf_msix_tablesize_pf3 |
0 |
| m1_dm_exvf_msixtable_offset_pf3 |
0 |
| m1_dm_exvf_msixtable_bir_pf3 |
0 |
| m1_dm_exvf_msixpba_offset_pf3 |
0 |
| m1_dm_exvf_msixpba_bir_pf3 |
0 |
| m1_dm_virtual_pf4_exvf_msix_cap_enable_hwtcl |
0 |
| m1_dm_exvf_msix_tablesize_pf4 |
0 |
| m1_dm_exvf_msixtable_offset_pf4 |
0 |
| m1_dm_exvf_msixtable_bir_pf4 |
0 |
| m1_dm_exvf_msixpba_offset_pf4 |
0 |
| m1_dm_exvf_msixpba_bir_pf4 |
0 |
| m1_dm_virtual_pf5_exvf_msix_cap_enable_hwtcl |
0 |
| m1_dm_exvf_msix_tablesize_pf5 |
0 |
| m1_dm_exvf_msixtable_offset_pf5 |
0 |
| m1_dm_exvf_msixtable_bir_pf5 |
0 |
| m1_dm_exvf_msixpba_offset_pf5 |
0 |
| m1_dm_exvf_msixpba_bir_pf5 |
0 |
| m1_dm_virtual_pf6_exvf_msix_cap_enable_hwtcl |
0 |
| m1_dm_exvf_msix_tablesize_pf6 |
0 |
| m1_dm_exvf_msixtable_offset_pf6 |
0 |
| m1_dm_exvf_msixtable_bir_pf6 |
0 |
| m1_dm_exvf_msixpba_offset_pf6 |
0 |
| m1_dm_exvf_msixpba_bir_pf6 |
0 |
| m1_dm_virtual_pf7_exvf_msix_cap_enable_hwtcl |
0 |
| m1_dm_exvf_msix_tablesize_pf7 |
0 |
| m1_dm_exvf_msixtable_offset_pf7 |
0 |
| m1_dm_exvf_msixtable_bir_pf7 |
0 |
| m1_dm_exvf_msixpba_offset_pf7 |
0 |
| m1_dm_exvf_msixpba_bir_pf7 |
0 |
| m2_mode_hwtcl |
BAM |
| m2_pf0_num_dma_chan_pf_hwtcl |
4 |
| m2_enable_32bit_address_hwtcl |
0 |
| m2_enable_user_hip_reconfig_sel_hwtcl |
0 |
| m2_enable_user_cii_hwtcl |
0 |
| m2_mc_pf0_bar0_type_user_hwtcl |
64-bit prefetchable memory |
| m2_mc_pf0_bar0_address_width_user_hwtcl |
16 |
| m2_mc_pf0_bar1_type_user_hwtcl |
Disabled |
| m2_mc_pf0_bar2_type_user_hwtcl |
Disabled |
| m2_mc_pf0_bar3_type_user_hwtcl |
Disabled |
| m2_mc_pf0_bar4_type_user_hwtcl |
Disabled |
| m2_mc_pf0_bar5_type_user_hwtcl |
Disabled |
| m2_mc_pf0_expansion_base_address_register_hwtcl |
0 |
| m3_mode_hwtcl |
BAM |
| m3_pf0_num_dma_chan_pf_hwtcl |
4 |
| m3_enable_32bit_address_hwtcl |
0 |
| m3_enable_user_hip_reconfig_sel_hwtcl |
0 |
| m3_enable_user_cii_hwtcl |
0 |
| m3_mc_pf0_bar0_type_user_hwtcl |
64-bit prefetchable memory |
| m3_mc_pf0_bar0_address_width_user_hwtcl |
16 |
| m3_mc_pf0_bar1_type_user_hwtcl |
Disabled |
| m3_mc_pf0_bar2_type_user_hwtcl |
Disabled |
| m3_mc_pf0_bar3_type_user_hwtcl |
Disabled |
| m3_mc_pf0_bar4_type_user_hwtcl |
Disabled |
| m3_mc_pf0_bar5_type_user_hwtcl |
Disabled |
| m3_mc_pf0_expansion_base_address_register_hwtcl |
0 |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |