Spartan 3E Starter Kit VHDL project

Demo application for testing the Spartan 3E Starter Kit. Download source and Xilinx ISE 8.2 project.

This application listens to the RS232 port and has the following functions:

• every char on RS232 is echoed (DCE port; you can change this to DTE in test.vhd)
• char "i" on RS232 sends the unique ROM id of the DS2432 as hex numbers
• char "1" on RS232 turns on LED 1 to 7
• char "0" on RS232 turns off LED 1 to 7
• LED 0 is blinking at 1 hz

To test it, start a terminal program, like HyperTerminal on Windows or Minicom on Linux, and set the communication parameters to 115,200 baud, no flow control and 8N1. When you type "i", you should receive something like "i000000e4ec2910", but with your DS2432 ROM id.

Synthesizing and Uploading with ISE 8.2

• double click the ise/Spartan3E.ise file
• right mouse click on "test" and "Set as Top Module"
• open the tree "Generate Programming File" in the Processes window
• double click on "Configure Device (iPACT)"

Now it needs some minutes to create the bit-file. Then iMPACT will be started:

• click on "Finish" for starting the JTAG Boundary Scan
• you'll see 3 devices and a file open dialog prompts for "Assign New Configuration File", which is for the first device, the FPGA itself. Double click on "test.bit"
• ignore the Startup Clock change warning by clicking on "ok"
• click on "Bypass" for the other two devices.
• click on the xc3s500e device
• double click on "Program" in the left iMPACT Processes window
• click on "ok"

When you close iMPACT, answer "Yes" to the question if you want to save your changes. This creates a Spartan3E.ipf file and you don't need to assign and bypass the JTAG files when starting iMPACT again.

If you have some problems with old projects, like I had, delete all xil_* file in the "c:\Documents and Settings\USER\Local Settings\Temp\" directory ("c:\Dokumente und Einstellungen\USER\Lokale Einstellungen\Temp\" for german users and where USER is your Windows logon name) before opening the Spartan3E.ise file.

Reusable entities

The VHDL entities are tested on the Spartan 3E Starter Kit, but can be used with other FPGAs and boards, too.

RS232 sender and receiver

The RS232 sender and receiver have a Whishbone interface. An program which echos all received data at 115,200 baud looks like this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
  port(
    clk_50mhz: in std_logic;
    rs232_dce_txd: out std_logic;
    rs232_dce_rxd: in std_logic);
end entity test;

architecture rtl of test is
  constant system_speed: natural := 50e6;
  constant baudrate: natural := 115200;

  signal rs232_ack: std_logic := '0';
  signal rs232_dat: unsigned(7 downto 0) := (others => '0');
  signal rs232_stb: std_logic := '0';

begin

  sender: entity rs232_sender
    generic map(system_speed, baudrate)
    port map(
      ack_o => rs232_ack,
      clk_i => clk_50mhz,
      dat_i => rs232_dat,
      rst_i => '0',
      stb_i => rs232_stb,
      tx => rs232_dce_txd);

  receiver: entity rs232_receiver
    generic map(system_speed, baudrate)
    port map(
      ack_i => rs232_ack,
      clk_i => clk_50mhz,
      dat_o => rs232_dat,
      rst_i => '0',
      stb_o => rs232_stb,
      rx => rs232_dce_rxd);

end architecture rtl;

DS2432 ROM id reader

This entity reads the ROM id of the DS2432 IC on the Spartan 3E Starter Kit over a 1-wire interface. Use it like this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
  port(
    ds_wire: inout std_logic;
    clk_50mhz: in std_logic);
end entity test;

architecture rtl of test is
  constant system_speed: natural := 50e6;

  signal ds_2432_rom: unsigned(47 downto 0) := (others => '0');
  signal ds_2432_rom_valid: std_logic := '0';
  
begin

  ds2432_inst: entity ds2432
    generic map(system_speed)
    port map(
      clk_i => clk_50mhz,
      rst_i => '0',
      rom_id_o => ds_2432_rom,
      data_valid_o => ds_2432_rom_valid,
      wire_io => ds_wire);

  ds_2432_rom_dump: process(clk_50mhz)
    variable digit: natural range 0 to 15;
  begin
    if rising_edge(clk_50mhz) then
      if ds_2432_rom_valid = '1' then
        -- do something with ds_2432_rom
      end if;
    end if;
  end process;
  
end architecture rtl;